Agusta; Joseph B. - US Patent Attorneys and Agents

Attorney: Agusta; Joseph B.

Number of patents: 28
Last date: December 13, 2011

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Number	Title	Issue Date
8077019	Method of associating groups of classified source addresses with vibration patterns In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to a...	12/13/2011
7567096	Circuit device and method of controlling a voltage swing In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activat...	07/28/2009
7526633	Method and system for encoding variable length packets with variable instruction sizes Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encodin...	04/28/2009
7523295	Processor and method of grouping and executing dependent instructions in a packet An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steeri...	04/21/2009
7502911	Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. P...	03/10/2009
7500045	Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus...	03/03/2009
7499347	Self-timing circuit with programmable delay and programmable accelerator circuits A memory has a novel self-timing circuit that generates internal memory control signals. Control signals may include an address latch enable signal, a decoder enable signal, and a sense amplifier enable signal. The circuit has a timing loop whose timing mimics the t...	03/03/2009
7478228	Apparatus for generating return address predictions for implicit and explicit subroutine calls An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode ...	01/13/2009
7466620	System and method for low power wordline logic for a memory A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of...	12/16/2008
7454607	Techniques for managing applications in a portable communication device An arbitration engine manages applications in a portable communication device by identifying a comprehensive DSP image that includes all modules necessary to run a new application as well as currently active applications. The arbitration engine also includes a confl...	11/18/2008
7454538	Latency insensitive FIFO signaling protocol Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in...	11/18/2008
7450963	Low power dual processor architecture for multi mode devices A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode...	11/11/2008
7444501	Methods and apparatus for recognizing a subroutine call An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the nex...	10/28/2008
7426626	TLB lock indicator A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access ...	09/16/2008
7421568	Power saving methods and apparatus to selectively enable cache bits based on known processor state A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer leng...	09/02/2008
7421529	Method and apparatus to clear semaphore reservation for exclusive access to shared memory Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a c...	09/02/2008
7415638	Pre-decode error handling via branch correction In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is force...	08/19/2008
7398371	Shared translation look-aside buffer and method A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts,...	07/08/2008
7376815	Methods and apparatus to insure correct predecode Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest le...	05/20/2008
7376032	Method and apparatus for a dummy SRAM cell A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same fir...	05/20/2008
7353319	Method and apparatus for segregating shared and non-shared data in cache memory banks In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or non-shared data accesses are directed to one or more banks designated f...	04/01/2008
7330941	Global modified indicator to reduce power consumption on cache miss A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-...	02/12/2008
7278012	Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting bran...	10/02/2007
7251192	Register read for volatile memory Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timin...	07/31/2007
7249210	Bus access arbitration scheme A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight...	07/24/2007
7246188	Flow control method to improve bus utilization in a system-on-a-chip integrated circuit A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the request...	07/17/2007
7242624	Methods and apparatus for reading a full-swing memory array Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the ...	07/10/2007
6865483	Methods and apparatus for providing a topology view based on heuristic information density A technique is provided to display a view perspective of an electronic map containing a number of viewable points of interest about a point of reference. The technique assigns a weighted importance value to each point of interest. Before displaying the view perspect...	03/08/2005

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Attorney: Agusta; Joseph B.