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| Number | Title | Issue Date |
| 8182978 | Developable bottom antireflective coating compositions especially suitable for ion implant applications Compositions characterized by the presence of an aqueous base-soluble polymer having aromatic moieties and aliphatic alcohol moieties have been found which are especially useful as developable bottom antireflective coatings in 193 nm lithographic processes. The comp... | 05/22/2012 |
| 8178931 | Bridge for semiconductor internal node A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a ... | 05/15/2012 |
| 8168971 | Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET... | 05/01/2012 |
| 8168489 | High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown ... | 05/01/2012 |
| 8138037 | Method and structure for gate height scaling with high-k/metal gate technology A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate me... | 03/20/2012 |
| 8131967 | Asynchronous data interface An interface system is disclosed. In one embodiment, the system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock ... | 03/06/2012 |
| 8127157 | System and method of controlling an operating frequency in an electronic system A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum opera... | 02/28/2012 |
| 8115275 | Electrical antifuse An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconduct... | 02/14/2012 |
| 8110496 | Method for performing chemical shrink process over BARC (bottom anti-reflective coating) A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and ha... | 02/07/2012 |
| 8110464 | SOI protection for buried plate implant and DT bottle ETCH An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a de... | 02/07/2012 |
| 8099688 | Circuit design A design process includes inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, and using a computer to translate the circuit design into a netlist. The netlist comprises a representation of a plurality of wires... | 01/17/2012 |
| 8097401 | Self-forming top anti-reflective coating compositions and, photoresist mixtures and method of imaging using same A composition of matter. The composition of matter includes a polymer having an ethylenic backbone and comprising a first monomer having an aromatic moiety, a second monomer having a base soluble moiety or an acid labile protected base soluble moiety, and a third mo... | 01/17/2012 |
| 8093657 | Circuit and methods to improve the operation of SOI devices According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse t... | 01/10/2012 |
| 8078852 | Predictors with adaptive prediction threshold An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter ... | 12/13/2011 |
| 8040813 | Apparatus and method for reduced loading of signal transmission elements An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling elemen... | 10/18/2011 |
| 8035126 | One-transistor static random access memory with integrated vertical PNPN device A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A bas... | 10/11/2011 |
| 8024679 | Structure for apparatus for reduced loading of signal transmission elements A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling eleme... | 09/20/2011 |
| 8013392 | High mobility CMOS circuits Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A f... | 09/06/2011 |
| 8008724 | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS tr... | 08/30/2011 |
| 7999377 | Method and structure for optimizing yield of 3-D chip manufacture The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both de... | 08/16/2011 |
| 7998828 | Method of forming metal ion transistor A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first ele... | 08/16/2011 |
| 7996618 | Apparatus and method for using branch prediction heuristics for determination of trace formation readiness A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on ini... | 08/09/2011 |
| 7982475 | Structure and method for reliability evaluation of FCPBGA substrates for high power semiconductor packaging applications There is provided a method for measuring thermal properties of a semiconductor packaging material. The method includes incorporating at least one conducting feature into a substrate that includes the semiconductor packaging material, applying an electric current to ... | 07/19/2011 |
| 7964865 | Strained silicon on relaxed sige film with uniform misfit dislocation density A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe la... | 06/21/2011 |
| 7961032 | Method of and structure for recovering gain in a bipolar transistor A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the ... | 06/14/2011 |
| 7960809 | eFuse with partial SiGe layer and design structure therefor A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region. ... | 06/14/2011 |
| 7955928 | Structure and method of fabricating FinFET A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material ha... | 06/07/2011 |
| 7934081 | Apparatus and method for using branch prediction heuristics for determination of trace formation readiness A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on ini... | 04/26/2011 |
| 7932136 | Source/drain junction for high performance MOSFET formed by selective EPI process In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension feat... | 04/26/2011 |
| 7928443 | Method and structure for forming strained SI for CMOS devices A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The s... | 04/19/2011 |
| 7923815 | DRAM having deep trench capacitors with lightly doped buried plates By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration ... | 04/12/2011 |
| 7923782 | Hybrid SOI/bulk semiconductor transistors Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technolog... | 04/12/2011 |
| 7913202 | Wafer level I/O test, repair and/or customization enabled by I/O layer A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions cir... | 03/22/2011 |
| 7898003 | Hybrid strained orientated substrates and devices A semiconductor structure. The structure includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from th... | 03/01/2011 |
| 7847358 | High performance strained CMOS devices A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is se... | 12/07/2010 |
| 7846791 | Structure for a trench capacitor A design structure of a trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The design structure resulting from the means for fabricating the trench cap... | 12/07/2010 |
| 7875919 | Shallow trench capacitor compatible with high-K / metal gate Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well... | 01/25/2011 |
| 7863123 | Direct contact between high-κ/metal gate and wiring process flow A low resistance contact is formed to a metal gate or a transistor including a High-κ gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill mate... | 01/04/2011 |
| 7859025 | Metal ion transistor A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from eac... | 12/28/2010 |
| 7838932 | Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transis... | 11/23/2010 |
