Abate, Esq.; Joseph P. - US Patent Attorneys and Agents

Attorney: Abate, Esq.; Joseph P.

Number of patents: 189
Last date: May 22, 2012

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Number	Title	Issue Date
8184465	Programmable semiconductor device A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first ...	05/22/2012
8173531	Structure and method to improve threshold voltage of MOSFETS including a high K dielectric A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon o...	05/08/2012
8159247	Yield enhancement for stacked chips through rotationally-connecting-interposer A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer prov...	04/17/2012
8159060	Hybrid bonding interface for 3-dimensional chip integration Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. T...	04/17/2012
8138100	Microelectronic structure by selective deposition A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall ...	03/20/2012
8133781	Method of forming a buried plate by ion implantation A mask layer formed over a semiconductor substrate is lithographically patterned to form an opening therein. Ions are implanted at an angle that is normal to the surface of the semiconductor substrate through the opening and into an upper portion of the semiconducto...	03/13/2012
8120095	High-density, trench-based non-volatile random access SONOS memory SOC applications The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine r...	02/21/2012
8108197	Method to verify an implemented coherency algorithm of a multi processor environment A coherency algorithm for a multi processor environment to run on a single processor model is verified by: generating a reference model reflecting a private cache hierarchy of a single processor within the multi processor environment, stimulating the private cache h...	01/31/2012
8078995	Efficient isotropic modeling approach to incorporate electromagnetic effects into lithographic process simulations Modeling of lithographic processes for use in the design of photomasks for the manufacture of semiconductor integrated circuits, and particularly to the modeling of the complex effects due to interaction of the illuminating light with the mask topography, is provide...	12/13/2011
8058157	FinFET structure with multiply stressed gate electrode A semiconductor structure and its method of fabrication include a semiconductor fin located over a substrate. A gate electrode is located over the semiconductor fin. The gate electrode has a first stress in a first region located closer to the semiconductor fin and ...	11/15/2011
8053809	Device including high-K metal gate finfet and resistive structure and method of forming thereof A device is provided that in one embodiment includes a substrate having a first region and a second region, in which a semiconductor device is present on a dielectric layer in the first region of the substrate and a resistive structure is present on the dielectric l...	11/08/2011
8036537	Optical pulse amplication apparatus and method A method and apparatus for producing a series of amplified optical pulses from a series of input optical pulses including creating a set of local optical pulses from a series of input optical pulses, the set of local optical pulses having different amplitudes arrang...	10/11/2011
8036243	Single chip protocol converter A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output the...	10/11/2011
8030709	Metal gate stack and semiconductor gate stack for CMOS devices A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed ...	10/04/2011
8022543	Underbump metallurgy for enhanced electromigration resistance A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer ...	09/20/2011
8009461	SRAM device, and SRAM device design structure, with adaptable access transistors A semiconductor device includes a SRAM having a pair of MCSFETs connected as access transistors (pass gates). A design structure embodied or stored in a machine readable medium includes a SRAM having two MCSFETs connected as access transistors. ...	08/30/2011
8008713	Vertical SOI trench SONOS cell A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access me...	08/30/2011
8004059	eFuse containing SiGe stack An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium di...	08/23/2011
7993990	Multiple crystallographic orientation semiconductor structures A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant pola...	08/09/2011
7989922	Highly tunable metal-on-semiconductor trench varactor An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor materia...	08/02/2011
7982285	Antifuse structure having an integrated heating element The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the...	07/19/2011
7981751	Structure and method for fabricating self-aligned metal contacts A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal...	07/19/2011
7979815	Compact model methodology for PC landing pad lithographic rounding impact on device performance A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the cond...	07/12/2011
7960801	Gate electrode stress control for finFET performance enhancement description A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an i...	06/14/2011
7960237	Structure and method for mosfet with reduced extension resistance The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of t...	06/14/2011
7947557	Heterojunction tunneling field effect transistors, and methods for fabricating the same The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a firs...	05/24/2011
7943493	Electrical fuse having a fully silicided fuselink and enhanced flux divergence A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an...	05/17/2011
7943457	Dual metal and dual dielectric integration for metal high-k FETs The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop ...	05/17/2011
7939894	Isolated high performance FET with a controllable body resistance The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and...	05/10/2011
7935993	Semiconductor device structure having enhanced performance FET device A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain r...	05/03/2011
7917729	System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con...	03/29/2011
7910451	Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor A node dielectric, an inner electrode, and a buried strap cavity are formed in the deep trench in an SOI substrate. A buried layer contact cavity is formed by lithographic methods. The buried strap cavity and the buried layer contact cavity are filled simultaneously...	03/22/2011
7884448	High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfac...	02/08/2011
7881093	Programmable precision resistor and method of programming the same A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a seco...	02/01/2011
7880266	Four-terminal antifuse structure having integrated heating elements for a programmable circuit The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the...	02/01/2011
7872897	Programmable semiconductor device A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first ...	01/18/2011
7865380	Automated information technology management system System and process for managing an IT infrastructure which collects transaction information on a component basis. The transaction data is used to evaluate the contribution of each component of the system as well as the business value of the service, and for the infr...	01/04/2011
7863197	Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tens...	01/04/2011
7859044	Partially gated FINFET with gate dielectric on only one sidewall A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the...	12/28/2010
7843024	Method and structure for improving device performance variation in dual stress liner technology A method and semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, are provided. In accordance with the present invention, the dual stress liner boundary or gap ther...	11/30/2010

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Attorney: Abate, Esq.; Joseph P.