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| Application No. | Application Title | Issue Date |
| 20110026173 | ENHANCED IMMUNITY FROM ELECTROSTATIC DISCHARGE Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second tra... | 02/03/2011 |
| 20110012633 | APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts... | 01/20/2011 |
| 20100322352 | SPHERE DETECTOR PERFORMING DEPTH-FIRST SEARCH UNTIL TERMINATED Systems and methods detect a communication received at receiving antennas from transmitting antennas. Each transmitting antenna transmits a symbol in a constellation. A sphere detector performs a depth-first search until the depth-first search terminates in response to ... | 12/23/2010 |
| 20100308910 | APPARATUS AND METHOD FOR PREDICTIVE OVER-DRIVE DETECTION A method and apparatus for efficient drive level selection for, e.g., power amplifiers utilized within a wireless communication system, which utilizes digital predistortion (DPD) to adaptively and predictively select drive level. The DPD, e.g., increases the power ampli... | 12/09/2010 |
| 20100272195 | PEAK-TO-AVERAGE POWER RATIO REDUCTION WITH BOUNDED ERROR VECTOR MAGNITUDE Method and apparatus for signal processing to minimize the peak to average power ratio of an Orthogonal Frequency Division Multiplexing (“OFDM”) or Orthogonal Frequency Division Multiple Access (“OFDMA”) signal with bounded error vector magnitude for an integrat... | 10/28/2010 |
| 20100258877 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-... | 10/14/2010 |
| 20100201883 | INTEGRATED CIRCUIT HAVING A CIRCUIT FOR AND METHOD OF PROVIDING INTENSITY CORRECTION FOR A VIDEO A method of providing intensity correction for a video is disclosed. The method may comprise evaluating a portion of a frame of the video; determining a difference in intensity of a current block of the frame with the corresponding block of the previous frame; correctin... | 08/12/2010 |
| 20100199136 | METHOD AND APPARATUS FOR DETECTING AND CORRECTING ERRORS IN A PARALLEL TO SERIAL CIRCUIT A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion ... | 08/05/2010 |
| 20100193870 | TECHNIQUES FOR IMPROVING TRANSISTOR-TO-TRANSISTOR STRESS UNIFORMITY An integrated circuit (100) has a transistor with an active gate structure 108 overlying an active diffusion area 112 formed in a semiconductor substrate 126. A dummy gate structure 110 is formed over a diffusion area and separated fro... | 08/05/2010 |
| 20100193229 | BARRIER LAYER TO PREVENT CONDUCTIVE ANODIC FILAMENTS A through hole is formed in a circuit board (300) that has fibers (312) dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating (308) over the sputtered copper layer... | 08/05/2010 |
| 20100192118 | METHOD OF AND CIRCUIT FOR IMPLEMENTING A FILTER IN AN INTEGRATED CIRCUIT According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzin... | 07/29/2010 |
| 20100191786 | DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the... | 07/29/2010 |
| 20100188787 | METHOD AND APPARATUS TO REDUCE FOOTPRINT OF ESD PROTECTION WITHIN AN INTEGRATED CIRCUIT An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the... | 07/29/2010 |
| 20100188142 | CIRCUIT FOR AND METHOD OF REDUCING POWER CONSUMPTION IN INPUT PORTS OF AN INTEGRATED CIRCUIT A circuit for reducing power consumption in input ports of an integrated circuit is disclosed. The circuit comprises a plurality of receiver circuits of the integrated circuit for receiving input signals coupled to the integrated circuit; and a bias current generator co... | 07/29/2010 |
| 20100183081 | GENERIC BUFFER CIRCUITS AND METHODS FOR OUT OF BAND SIGNALING Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals ... | 07/22/2010 |
| 20100142243 | DATA STORAGE SYSTEM WITH REMOVABLE MEMORY MODULE HAVING PARALLEL CHANNELS OF DRAM MEMORY AND FLASH MEMORY A data storage system 400 includes a first circuit board 401, a plurality of sockets 402 coupled to the first circuit board 401, an connector 403 coupled to each of the sockets 402 for coupling each of the sockets 402 to ... | 06/10/2010 |
| 20100127782 | Common Centroid Electrostatic Discharge Protection for Integrated Circuit Devices A method of protecting a circuit design implemented within an integrated circuit (IC) from electrostatic discharge (ESD) can include positioning a device array pair comprising first and second device arrays on the IC to share a common centroid, wherein the first and sec... | 05/27/2010 |
| 20100127351 | INTEGRATED CAPACITOR WITH INTERLINKED LATERAL FINS A capacitor in an integrated circuit (“IC”) has a first node conductor formed in a first metal layer of the IC with a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to the... | 05/27/2010 |
| 20100127349 | INTEGRATED CAPACITOR WITH ARRAY OF CROSSES A capacitor in an integrated circuit (“IC”) has a first plurality of conductive crosses formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses formed in the metal laye... | 05/27/2010 |
| 20100127348 | INTEGRATED CAPICITOR WITH CABLED PLATES A capacitor in an integrated circuit (“IC”) has a distribution grid formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament connected to and extending away from the distribution grid along a first direction. A secon... | 05/27/2010 |
| 20100127347 | SHIELDING FOR INTEGRATED CAPACITORS A capacitor in an integrated circuit (“IC”) includes a core capacitor portion having first conductive elements electrically connected to and forming a part of a first node of the capacitor formed in a first layer and second conductive elements electrically connected... | 05/27/2010 |
| 20100127309 | INTEGRATED CAPACITOR WITH ALTERNATING LAYERED SEGMENTS A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed in a... | 05/27/2010 |
| 20100079182 | METHOD AND APPARATUS FOR COUNTER-BASED CLOCK SIGNAL ADAPTATION A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal... | 04/01/2010 |
| 20100070737 | ADDRESS GENERATION Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to pr... | 03/18/2010 |
| 20100052780 | METHOD OF AND CIRCUIT FOR REDUCING DISTORTION IN A POWER AMPLIFIER An integrated circuit having a circuit for reducing distortion in a power amplifier is disclosed. The integrated circuit comprises a predistortion circuit coupled to receive a signal to be amplified; sample capture buffers coupled to an output of the predistortion circu... | 03/04/2010 |
| 20100040177 | MIMO Symbol Detection for SNR Higher and Lower than a Threshold A system detects symbols communicated from multiple transmitting antennas to multiple receiving antennas. A first detector determines the symbols from respective partial distances of potential choices for symbols from a constellation. A second detector determines the sy... | 02/18/2010 |
| 20100008451 | Symbol Detection in a MIMO Communication System Circuits are provided for detecting symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A circuit includes distance blocks, selectors, and an identifier block. Each distance-block includes at least one sub-block, and each sub-block in... | 01/14/2010 |
| 20100007565 | Detecting In-Phase and Quadrature-Phase Amplitudes of MIMO Communications Circuits detect communications from multiple transmitting antennas to multiple receiving antennas. A respective first block for each non-initial transmitting antenna determines partial distances for pairings of a first candidate and a quadrature-phase amplitude. A respe... | 01/14/2010 |
| 20090290071 | CIRCUIT FOR AND METHOD OF RECEIVING VIDEO DATA A circuit of an integrated circuit for receiving video data having a plurality of data streams of pixel data and a pixel clock is disclosed. The circuit comprises a plurality of data recovery circuits, each data recovery circuit coupled to receive a corresponding data s... | 11/26/2009 |
| 20090289667 | Clock Generation Using a Fractional Phase Detector Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output cloc... | 11/26/2009 |
| 20090276599 | CONFIGURABLE TRANSACTIONAL MEMORY FOR SYNCHRONIZING TRANSACTIONS A configurable transactional memory synchronizes transactions from clients. The configurable transactional memory includes a memory buffer and a transactional buffer. The memory buffer includes allocation control and storage, and the allocation control is configurable t... | 11/05/2009 |
| 20090249024 | Address generation for quadratic permutation polynomial interleaving For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for o... | 10/01/2009 |
| 20090235222 | CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist (110), mapping logic gates of the netlist to functionally equiv... | 09/17/2009 |
| 20090232254 | Detector Using Limited Symbol Candidate Generation for MIMO Communication Systems A circuit detects symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A distance block for an initial transmitting antenna in an ordering of the transmitting antennas determines a distance value for each symbol in a constellation. A s... | 09/17/2009 |
| 20090224400 | SEMICONDUCTOR ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE AND METHODS OF MAKING SAME Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A hea... | 09/10/2009 |
| 20090224323 | INTEGRATED CIRCUIT WITH MOSFET FUSE ELEMENT At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse res... | 09/10/2009 |
| 20090213947 | BLOCK BOUNDARY DETECTION FOR A WIRELESS COMMUNICATION SYSTEM Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template inc... | 08/27/2009 |
| 20090213946 | PARTIAL RECONFIGURATION FOR A MIMO-OFDM COMMUNICATION SYSTEM Partial reconfiguration of programmable logic for supporting a Multiple-input, Multiple-Output Orthogonal Frequency Division Multiplexing (“MIMO-OFDM”) communication system is described. A PHY block in a programmable device may be instantiated generally in part in p... | 08/27/2009 |
| 20090210731 | CIRCUIT FOR AND METHOD OF MINIMIZING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT DEVICE A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plu... | 08/20/2009 |
| 20090173520 | Reduction of jitter in a semiconductor device by controlling printed ciucuit board and package substrate stackup A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering j... | 07/09/2009 |
