Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Application No. | Application Title | Issue Date |
| 20090132939 | METHOD AND APPARATUS FOR A FLOATING ISLAND FOR USER NAVIGATION IN AN INTERACTIVE ENVIRONMENT This invention provides a method for dynamically calculating and presenting a graphical user interface (GUI) within the display device in a computing system including a display device and an input device. The method includes creating a shared icon space within the GUI, ... | 05/21/2009 |
| 20090132732 | UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT A universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling prot... | 05/21/2009 |
| 20090127626 | STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at le... | 05/21/2009 |
| 20090112954 | A ROBUST SPECTRAL ANALYZER FOR ONE-DIMENSIONAL AND MULTI-DIMENSIONAL DATA ANALYSIS A method of analyzing a spectrum of one-dimensional or multi-dimensional signal X(t) requires a number of steps including deriving coefficients [AN(ω), BN(ω)] of an Lp-norm harmonic regression of tie signal with 0<p≦∞ and pγ2, squaring th... | 04/30/2009 |
| 20090112841 | DOCUMENT SEARCHING USING CONTEXTUAL INFORMATION LEVERAGE AND INSIGHTS A method and system are disclosed that enable a user to search a large collection of structured and unstructured documents using semantic concepts that the system provides to them, to search the most relevant business activity first, and then using one of the business a... | 04/30/2009 |
| 20090111228 | SELF ALIGNED RING ELECTRODES The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a... | 04/30/2009 |
| 20090111225 | CMOS STRUCTURE AND METHOD INCLUDING MULTIPLE CRYSTALLOGRAPHIC PLANES A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa h... | 04/30/2009 |
| 20090110898 | HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE A method of forming a semiconductor-on-insulator (SOI) substrate using a thermal annealing process to provide a semiconductor base wafer having a thin high resistivity surface layer that is positioned at the interface with the buried insulating layer is provided. Specif... | 04/30/2009 |
| 20090108472 | WAFER-LEVEL UNDERFILL PROCESS USING OVER-BUMP-APPLIED RESIN A process of fabricating wafer-level underfilled microelectronic packages using over-bump application of a self-fluxing resin to a wafer, b-staging of the resin, dicing of the coated wafer, and joining the diced chips to substrates producing wafer-level underfilled micr... | 04/30/2009 |
| 20090108400 | ANTI-FUSE STRUCTURE INCLUDING A SENSE PAD CONTACT REGION AND METHODS FOR FABRICATION AND PROGRAMMING THEREOF An antifuse structure includes a sense pad contact region that is separate from an anode contact region and a cathode contact region. By including the sense pad contact region that is separate from the anode contact region and the cathode contact region, a programming c... | 04/30/2009 |
| 20090108396 | ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upp... | 04/30/2009 |
| 20090108378 | STRUCTURE AND METHOD FOR FABRICATING SELF-ALIGNED METAL CONTACTS A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal sem... | 04/30/2009 |
| 20090108372 | SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different... | 04/30/2009 |
| 20090108356 | INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function... | 04/30/2009 |
| 20090108355 | SOI CMOS CIRCUITS WITH SUBSTRATE BIAS The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a sil... | 04/30/2009 |
| 20090108347 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protec... | 04/30/2009 |
| 20090108324 | SEMICONDUCTOR FIN BASED NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATION THEREOF A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor fin having a first side and a second side opposite the first side. A first gate dielectric and a charge storage layer are successively layered upon the first side ... | 04/30/2009 |
| 20090108302 | MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity... | 04/30/2009 |
| 20090108301 | HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bon... | 04/30/2009 |
| 20090108294 | SCALABLE HIGH-K DIELECTRIC GATE STACK A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack... | 04/30/2009 |
| 20090108289 | DESIGN STRUCTURE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE A design structure for a circuit providing the same trigger voltage across the multiple fingers is provided, which comprises a data representing an external current injection source connected to individual fingers of a multi-finger semiconductor device. For example, the... | 04/30/2009 |
| 20090106815 | METHOD FOR MAPPING PRIVACY POLICIES TO CLASSIFICATION LABELS A method and system are disclosed for mapping a privacy policy into classification labels for controlling access to information on a computer system or network, said privacy policy including one or more rules for determining which users can access said information. The ... | 04/23/2009 |
| 20090106714 | METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-cur... | 04/23/2009 |
| 20090106011 | SYSTEM AND METHOD FOR DEVELOPING AND DEPLOYING SENSOR AND ACTUATOR APPLICATIONS OVER DISTRIBUTED COMPUTING INFRASTRUCTURE The present invention discloses a method for coordinating zero or more modelings, zero or more implementations and zero or more deployments of a computer system, including but not limited to computer systems involving sensors, actuators, or both and a system providing a... | 04/23/2009 |
| 20090102026 | SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH A DIFFUSION BARRIER A diffusion barrier layer is incorporated between a top semiconductor layer and buried oxide layer. The diffusion barrier layer blocks diffusion of dopants into or out of buried oxide layer. The diffusion barrier layer may comprise a dielectric material such as silicon ... | 04/23/2009 |
| 20090102019 | CONTROLLED DOPING OF SEMICONDUCTOR NANOWIRES A catalyst particle on a substrate is exposed to reactants containing a semiconductor material in a reactor. An intrinsic semiconductor nanowire having constant lateral dimensions is grown at a low enough temperature so that pyrolysis of the reactant is suppressed on th... | 04/23/2009 |
| 20090101995 | PROCESS FOR FABRICATION OF FINFETs A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width con... | 04/23/2009 |
| 20090101993 | HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxi... | 04/23/2009 |
| 20090101989 | METAL GATE COMPATIBLE ELECTRICAL FUSE A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing ... | 04/23/2009 |
| 20090101985 | TRILAYER RESIST SCHEME FOR GATE ETCHING APPLICATIONS A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme uti... | 04/23/2009 |
| 20090101956 | EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device r... | 04/23/2009 |
| 20090101941 | WRAPPED GATE JUNCTION FIELD EFFECT TRANSISTOR A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conduc... | 04/23/2009 |
| 20090100664 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cro... | 04/23/2009 |
| 20090100498 | METHOD AND SYSTEM FOR ANALYZING POLICIES FOR COMPLIANCE WITH A SPECIFIED POLICY USING A POLICY TEMPLATE A method and system are disclosed for analyzing policies for compliance with a specified policy. The method comprises the steps of creating a policy template representing said specified policy, and comparing a group of given policies to said policy template to determine... | 04/16/2009 |
| 20090100197 | PULSE-PER-SECOND ATTACHMENT FOR STP A time synchronization apparatus, method and system are provided. In one aspect, the apparatus comprises at least a time of day clock, a first port operable to receive at least first time information using a first time protocol, a second port operable to receive at leas... | 04/16/2009 |
| 20090098347 | PHOTOSENSITIVE SELF-ASSEMBLED MONOLAYER FOR SELECTIVE PLACEMENT OF HYDROPHILIC STRUCTURES A photosensitive monolayer is self-assembled on an oxide surface. The chemical compound of the photosensitive monolayer has three components. A first end group provides covalent bonds with the oxide surface for self assembly on the oxide surface. A photosensitive group ... | 04/16/2009 |
| 20090096102 | CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligne... | 04/16/2009 |
| 20090096059 | FUSE STRUCTURE INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL LAYER AND GAP A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a subs... | 04/16/2009 |
| 20090096003 | SEMICONDUCTOR CELL STRUCTURE INCLUDING BURIED CAPACITOR AND METHOD FOR FABRICATION THEREOF A semiconductor structure and a method for fabricating the semiconductor structure include at least one field effect transistor, and also a capacitor, located over a substrate. In particular, the capacitor is located interposed between the field effect transistor and th... | 04/16/2009 |
| 20090094441 | Perform Floating Point Operation Instruction A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprise the steps of obtaining a perform floating-point operation instruction; obtaining a test bit; and determining a value of the test bit. If the test bit ... | 04/09/2009 |
