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| Application No. | Application Title | Issue Date |
| 20110037772 | Scalable Unified Memory Architecture A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instruct... | 02/17/2011 |
| 20110029801 | Method and System for Balancing Receive-Side Supply Load Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensat... | 02/03/2011 |
| 20110019760 | Methods and Systems for Reducing Supply and Termination Noise A transmitter expresses continuous-time signals on alternate, parallel channels with reference to different supply voltages such that the signals on alternate channels have different common-mode voltages. At the transmitter, expressing the symbols using alternate supply... | 01/27/2011 |
| 20100318311 | Driver Calibration Methods and Circuits Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without int... | 12/16/2010 |
| 20100262790 | Memory Controllers, Methods, and Systems Supporting Multiple Memory Modes A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory device... | 10/14/2010 |
| 20100259295 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and m... | 10/14/2010 |
| 20100237903 | Configurable On-Die Termination Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or... | 09/23/2010 |
| 20100223426 | Variable-width memory Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of l... | 09/02/2010 |
| 20100215091 | Adaptive Equalization Using Correlation of Edge Samples With Data Patterns An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming d... | 08/26/2010 |
| 20100211748 | Memory System With Point-to-Point Request Interconnect A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory device... | 08/19/2010 |
| 20100142607 | Methods and Systems for Transmitting Data by Modulating Transmitter Filter Coefficients A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmit... | 06/10/2010 |
| 20100135378 | Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbo... | 06/03/2010 |
| 20100128542 | Reference Clock and Command Word Alignment A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock s... | 05/27/2010 |
| 20100085100 | Low-Power Clock Generation and Distribution Circuitry A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold ... | 04/08/2010 |
| 20100077267 | Memory System with Point-to-Point Request Interconnect A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory device... | 03/25/2010 |
| 20100077136 | Memory System Supporting Nonvolatile Physical Memory A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods ... | 03/25/2010 |
| 20100074314 | Margin Test Methods And Circuits Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference... | 03/25/2010 |
| 20100073047 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing referenc... | 03/25/2010 |
| 20100067314 | Memory Systems And Methods For Dynamically Phase Adjusting A Write Strobe And Data To Account For Receive-Clock Drift A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory dev... | 03/18/2010 |
| 20100066450 | High-Speed Low-Power Differential Receiver A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low-voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate conf... | 03/18/2010 |
| 20100061047 | Upgradable Memory System with Reconfigurable Interconnect Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or... | 03/11/2010 |
| 20100054323 | Adaptive Receive-Side Equalization An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measure... | 03/04/2010 |
| 20100050010 | Data-Width Translation Between Variable-Width and Fixed-Width Data Ports Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the widt... | 02/25/2010 |
| 20100046600 | Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compe... | 02/25/2010 |
| 20100046597 | Adaptive Receive-Side Equalization An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measure... | 02/25/2010 |
| 20100020861 | DFE Margin Test Methods and Circuits that Decouple Sample and Feedback Timing Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference... | 01/28/2010 |
| 20100008414 | High-Speed Signaling Systems And Methods With Adaptable, Continuous-Time Equalization A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) b... | 01/14/2010 |
| 20090278565 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and m... | 11/12/2009 |
| 20090243681 | Embedded Source-Synchronous Clock Signals A synchronous communication system includes two transmitters that transmit respective first and second data signals that are phase offset from one another by about 90 degrees. On the receive side, a pair of extraction circuits extract a first clock signal from the first... | 10/01/2009 |
| 20090103572 | Crosstalk Minimization in Serial Link Systems Described are methods and circuits for reducing the error-inducing effects of crosstalk. Communication circuits in accordance with some embodiments adjust the phase of transmitted “aggressor” data to misalign transmitted signals from the perspective of “victim” ... | 04/23/2009 |
| 20080303568 | Clock distribution network supporting low-power mode A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destinati... | 12/11/2008 |
| 20080263487 | Multi-Format Consistency Checking Tool A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examp... | 10/23/2008 |
| 20080240219 | Methods And Circuits For Performing Margining Tests In The Presence Of A Decision Feedback Equalizer Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE inje... | 10/02/2008 |
| 20080211536 | Driver calibration methods and circuits Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without int... | 09/04/2008 |
| 20080181348 | Apparatus for data recovery in a synchronous chip-to-chip system An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing referenc... | 07/31/2008 |
| 20070297520 | Noise-tolerant signaling schemes supporting simplified timing and data recovery Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very... | 12/27/2007 |
| 20070290714 | Calibration methods and circuits to calibrate drive current and termination impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and m... | 12/20/2007 |
| 20070253475 | Adaptive equalization using correlation of edge samples with data patterns An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming d... | 11/01/2007 |
| 20070159228 | Systems and methods for controlling termination resistance values for a plurality of communication channels Described are controllable termination impedances that may be adjusted collectively by a combination of digital and analog signals. Each adjustable impedance, responsive to the digital signals, establishes a gross termination resistance for one of a plurality of communi... | 07/12/2007 |
| 20070162668 | Variable-width memory module with fixed-width memory die Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the widt... | 07/12/2007 |
