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| Application No. | Application Title | Issue Date |
| 20090035101 | TWO-DIMENSIONAL TRANSFER STATION USED AS INTERFACE BETWEEN A PROCESS TOOL AND A TRANSPORT SYSTEM AND A METHOD OF OPERATING THE SAME By providing a space-efficient transfer buffer system in a manufacturing environment, which may act as a local interface between an automated transport system and the load port assembly of a process tool under consideration, the I/O capability of the process tool may be... | 02/05/2009 |
| 20090035102 | METHOD AND SYSTEM FOR LOCALLY BUFFERING SUBSTRATE CARRIERS IN AN OVERHEAD TRANSPORT SYSTEM FOR ENHANCING INPUT/OUTPUT CAPABILITIES OF PROCESS TOOLS By providing an overhead buffer system between an automatic transport system and a load port assembly of a process tool, the efficiency of the respective load ports may be significantly enhanced, for instance, by reducing the idle time of empty carriers, thereby providi... | 02/05/2009 |
| 20090001479 | TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME By removing an upper portion of a complex spacer structure, such as a triple spacer structure, an upper surface of an intermediate spacer element may be exposed, thereby enabling the removal of the outermost spacer and a material reduction of the intermediate spacer in ... | 01/01/2009 |
| 20090007028 | WAFER LAYOUT OPTIMIZATION METHOD AND SYSTEM For determining an optimized wafer layout, at least two wafer layouts are specified for a given wafer, each wafer layout defining the location of a plurality of die with regard to the wafer. An optimization parameter value of at least one optimization parameter is deter... | 01/01/2009 |
| 20080286966 | METHOD OF FORMING A DIELECTRIC CAP LAYER FOR A COPPER METALLIZATION BY USING A HYDROGEN BASED THERMAL-CHEMICAL TREATMENT A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based depos... | 11/20/2008 |
| 20080265426 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A... | 10/30/2008 |
| 20080265365 | METHOD FOR PREVENTING THE FORMATION OF ELECTRICAL SHORTS VIA CONTACT ILD VOIDS Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors m... | 10/30/2008 |
| 20080241756 | ENHANCING LITHOGRAPHY FOR VIAS AND CONTACTS BY USING DOUBLE EXPOSURE BASED ON LINE-LIKE FEATURES By performing a double exposure process on the basis of bar-like or line-like features, critical via and contact openings may be defined as an intersection, thereby obtaining the desired design dimension on the basis of less critical lithography process windows. Hence, ... | 10/02/2008 |
| 20080237712 | SOI TRANSISTOR HAVING DRAIN AND SOURCE REGIONS OF REDUCED LENGTH AND A STRESSED DIELECTRIC MATERIAL ADJACENT THERETO By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing... | 10/02/2008 |
| 20080242195 | CMP SYSTEM HAVING AN EDDY CURRENT SENSOR OF REDUCED HEIGHT By providing an eddy current sensor element in a polishing tool at a reduced height level in combination with a corresponding optical endpoint detection system, standard polishing pads may be used, thereby enhancing the lifetime of the polishing pad and increasing tool ... | 10/02/2008 |
| 20080206986 | METHOD OF FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAP LAYER BY AN ADVANCED INTEGRATION REGIME By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers ... | 08/28/2008 |
| 20080203486 | METHOD FOR DIFFERENTIAL SPACER REMOVAL BY WET CHEMICAL ETCH PROCESS AND DEVICE WITH DIFFERENTIAL SPACER STRUCTURE By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely... | 08/28/2008 |
| 20080203427 | SEMICONDUCTOR DEVICE HAVING A STRAINED SEMICONDUCTOR ALLOY CONCENTRATION PROFILE A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may b... | 08/28/2008 |
| 20080182409 | METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY ELECTROLESS DEPOSITION USING A SELECTIVELY PROVIDED ACTIVATION LAYER By forming an activation/nucleation layer selectively at a bottom of an opening, efficient electroless deposition techniques may be used for forming contacts, vias and trenches of advanced semiconductor devices. By selectively providing the activation material, a self-a... | 07/31/2008 |
| 20080179628 | TRANSISTOR WITH EMBEDDED SILICON/GERMANIUM MATERIAL ON A STRAINED SEMICONDUCTOR ON INSULATOR SUBSTRATE By combining a respectively adapted lattice mismatch between a first semiconductor material in a channel region and an embedded second semiconductor material in an source/drain region of a transistor, the strain transfer into the channel region is increased. According t... | 07/31/2008 |
| 20080182406 | METHOD OF FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAP LAYER BY AN ADVANCED INTEGRATION REGIME By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers ... | 07/31/2008 |
| 20080156641 | SYSTEM FOR DRIVING AND CONTROLLING A MOVABLE ELECTRODE ASSEMBLY IN AN ELECTROCHEMICAL PROCESS TOOL By providing an enhanced drive system for electrochemical etch process tools, the operational range, as well as the reliability, may be enhanced. For this purpose, a high torque electric motor may be used in combination with an appropriate power transmission, which may ... | 07/03/2008 |
| 20080160762 | METHOD FOR THE PROTECTION OF METAL LAYERS AGAINST EXTERNAL CONTAMINATION In order to avoid the contamination of a seed layer, which is typically highly reactive with the external atmosphere, during the formation of interconnect structures in a semiconductor device, a protective layer is formed. The protective layer may be comprised of oxide ... | 07/03/2008 |
| 20080160654 | METHOD OF TESTING AN INTEGRITY OF A MATERIAL LAYER IN A SEMICONDUCTOR STRUCTURE A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to ... | 07/03/2008 |
| 20080160650 | SYSTEM AND METHOD FOR CONTROLLING AN ELECTROCHEMICAL ETCH PROCESS By evaluating a status signal on the basis of a fault detection classification mechanism in an electrochemical etch tool, a corresponding failure status of the tool may be obtained for each single substrate, thereby significantly reducing the risk of significant yield l... | 07/03/2008 |
| 20080131796 | METHOD AND TEST STRUCTURE FOR ESTIMATING FOCUS SETTINGS IN A LITHOGRAPHY PROCESS BASED ON CD MEASUREMENTS By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluat... | 06/05/2008 |
| 20080132152 | METHOD AND SYSTEM FOR CONTROLLING CHEMICAL MECHANICAL POLISHING BY CONTROLLABLY MOVING A SLURRY OUTLET A system and a method of operating a chemical mechanical polishing (CMP) system comprises a slurry delivering unit configured for locally varying the supply of slurry while polishing the substrate. To this end, the slurry delivering unit may comprise at least one slurry... | 06/05/2008 |
| 20080132072 | SEMICONDUCTOR SUBSTRATE HAVING A PROTECTION LAYER AT THE SUBSTRATE BACK SIDE By forming a protection layer on the back side of a substrate prior to any process sequences, which may deposit material or material residues on the back side, the respective back side uniformity may be significantly enhanced, thereby also increasing process efficiency ... | 06/05/2008 |
| 20080090349 | DIFFERENT EMBEDDED STRAIN LAYERS IN PMOS AND NMOS TRANSISTORS AND A METHOD OF FORMING THE SAME By omitting a growth mask or by omitting lithographical patterning processes for forming growth masks, a significant reduction in process complexity may be obtained for the formation of different strained semiconductor materials in different transistor types. Moreover, ... | 04/17/2008 |
| 20080079085 | SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed ... | 04/03/2008 |
| 20080081480 | METHOD FOR REDUCING RESIST POISONING DURING PATTERNING OF SILICON NITRIDE LAYERS IN A SEMICONDUCTOR DEVICE By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantl... | 04/03/2008 |
| 20080081471 | TECHNIQUE FOR LOCALLY ADAPTING TRANSISTOR CHARACTERISTICS BY USING ADVANCED LASER/FLASH ANNEAL TECHNIQUES By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduce... | 04/03/2008 |
| 20080059527 | SYSTEM AND METHOD FOR STANDARDIZED PROCESS MONITORING IN A COMPLEX MANUFACTURING ENVIRONMENT By monitoring a process flow in a complex manufacturing environment on the basis of a technique using standardized data structures, process-related evaluated data structures corresponding to a process history of objects may be recorded with a high degree of coverage. Fu... | 03/06/2008 |
| 20080054415 | N-CHANNEL FIELD EFFECT TRANSISTOR HAVING A CONTACT ETCH STOP LAYER IN COMBINATION WITH AN INTERLAYER DIELECTRIC SUB-LAYER HAVING THE SAME TYPE OF INTRINSIC STRESS By forming a tensile silicon dioxide layer on the basis of a sub-atmospheric deposition technique, the strain-inducing mechanism of a tensile contact etch stop layer for N-channel transistors may be significantly improved. Consequently, for otherwise identical stress co... | 03/06/2008 |
| 20080023692 | TRANSISTOR HAVING A STRAINED CHANNEL REGION INCLUDING A PERFORMANCE ENHANCING MATERIAL COMPOSITION By forming a semiconductor alloy in a silicon-based active semiconductor region prior to the gate patterning, material characteristics of the semiconductor alloy itself may also be exploited in addition to the strain-inducing effect thereof. Consequently, device perform... | 01/31/2008 |
| 20080026572 | METHOD FOR FORMING A STRAINED TRANSISTOR BY STRESS MEMORIZATION BASED ON A STRESSED IMPLANTATION MASK By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.... | 01/31/2008 |
| 20080026531 | FIELD EFFECT TRANSISTOR AND METHOD OF FORMING A FIELD EFFECT TRANSISTOR A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least on... | 01/31/2008 |
| 20080026487 | METHOD OF FORMING AN ETCH INDICATOR LAYER FOR REDUCING ETCH NON-UNIFORMITIES By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advanta... | 01/31/2008 |
| 20080003830 | REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PROVIDING A PROTECTION LAYER AT THE SUBSTRATE EDGE By providing a protection layer at the bevel region, the deposition of polymer materials during the patterning process of complex metallization structures may be reduced. Additionally or alternatively, a surface topography may be provided, for instance in the form of re... | 01/03/2008 |
| 20080003825 | METHOD OF PATTERNING GATE ELECTRODES BY REDUCING SIDEWALL ANGLES OF A MASK LAYER By performing an anisotropic resist modification prior to the actual resist trimming process, the profile of the end portions of the resist features may be significantly enhanced, for instance by providing substantially vertical sidewall portions. Consequently, an overl... | 01/03/2008 |
| 20070278693 | METALLIZATION LAYER OF A SEMICONDUCTOR DEVICE HAVING DIFFERENTLY THICK METAL LINES AND A METHOD OF FORMING THE SAME A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provid... | 12/06/2007 |
| 20070282475 | METHOD AND SYSTEM FOR DETERMINING UTILIZATION OF PROCESS TOOLS IN A MANUFACTURING ENVIRONMENT BASED ON CHARACTERISTICS OF AN AUTOMATED MATERIAL HANDLING SYSTEM By determining a metric for tool utilization in a manufacturing environment on the basis of tool-specific characteristics and a probability distribution for the transport capability of an automated material handling system, the influence of the transport system on the t... | 12/06/2007 |
| 20070282477 | METHOD AND SYSTEM FOR CONTROLLING PROCESS TOOLS BY INTERRUPTING PROCESS JOBS DEPENDING ON JOB PRIORITY By enabling an interleaved mode when supplying substrates from a plurality of load ports to a respective process module, a reduction of non-productive time of the process tool and/or a reduction of cycle time may be achieved compared to a conventional sequential process... | 12/06/2007 |
| 20070282474 | METHOD AND SYSTEM FOR DYNAMICALLY CHANGING THE TRANSPORT SEQUENCING IN A CLUSTER TOOL By dynamically adapting the transport sequencing rules of a cluster tool, the overall performance of the tool may be increased. In some illustrative embodiments, the transport sequencing rule for a robot handler may be dynamically changed when a lot of small size is pre... | 12/06/2007 |
| 20070254441 | Method of forming a field effect transistor A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised dra... | 11/01/2007 |
