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| Application No. | Application Title | Issue Date |
| 20110037143 | Semiconductor Device Using An Aluminum Interconnect To Form Through-Silicon Vias An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate,... | 02/17/2011 |
| 20110034021 | PROGRAMMABLE THROUGH SILICON VIA Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent... | 02/10/2011 |
| 20110027948 | METHOD FOR MANUFACTURING A FINFET DEVICE A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the expos... | 02/03/2011 |
| 20110018575 | METHOD AND SYSTEM FOR ASSESSING RELIABILITY OF INTEGRATED CIRCUIT The present invention provides a method. The method includes operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a se... | 01/27/2011 |
| 20110016442 | Method of Performing Static Timing Analysis Considering Abstracted Cell's Interconnect Parasitics An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electric... | 01/20/2011 |
| 20110014757 | PROCESS INTEGRATION FOR FLASH STORAGE ELEMENT AND DUAL CONDUCTOR COMPLEMENTARY MOSFETS A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction can be deposited simultaneously with a first metal layer for... | 01/20/2011 |
| 20110001169 | FORMING UNIFORM SILICIDE ON 3D STRUCTURES By using a non-conformal diffusion barrier in conjunction with a similarly deposited non-conformal initial deposition of siliciding material, a substantially uniform and conformal silicide can be formed in a 3D structure such as the fin of a FinFET. The siliciding mater... | 01/06/2011 |
| 20100332193 | Method of Multi-segments Modeling Bond Wire Interconnects with 2D Simulations in High Speed, High Density Wire Bond Packages A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects... | 12/30/2010 |
| 20100330763 | METHOD OF CREATING ASYMMETRIC FIELD-EFFECT-TRANSISTORS The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respect... | 12/30/2010 |
| 20100327445 | STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being cover... | 12/30/2010 |
| 20100327430 | SEMICONDUCTOR DEVICE ASSEMBLY HAVING A STRESS-RELIEVING BUFFER LAYER Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface ma... | 12/30/2010 |
| 20100314689 | LOCAL METALLIZATION AND USE THEREOF IN SEMICONDUCTOR DEVICES An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semicond... | 12/16/2010 |
| 20100306723 | Order Independent Method of Performing Statistical N-Way Maximum/Minimum Operation for Non-Gaussian and Non-linear Distributions A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized u... | 12/02/2010 |
| 20100306603 | Segmented and Overlapped skew tracking method for serdes frame interface Level 5 A method and device for performing skew detection on data transmitted over a data channel and a high speed optical communication interface including the device are disclosed, wherein data of a reference frame over a reference channel is composed sequentially of a refere... | 12/02/2010 |
| 20100301331 | BODY CONTACT STRUCTURE FOR IN-LINE VOLTAGE CONTRAST DETECTION OF PFET SILICIDE ENCROACHMENT Test structures for in-line voltage contrast detection of PFET silicide encroachment defects are disclosed. Embodiments of the present invention provide for improved PFET test structures for detecting encroachment defects using VC imaging techniques. The test structures... | 12/02/2010 |
| 20100289645 | SYSTEM AND METHOD FOR SAFEGUARDING WAFERS AND PHOTOMASKS A system and a method for safeguarding wafers and photomasks. The system includes a container for storing an article, the article being a wafer or a photomask; a flashing unit for flashing light with a pre-determined light pattern; an anti-theft unit capable of performi... | 11/18/2010 |
| 20100289144 | 3D INTEGRATION STRUCTURE AND METHOD USING BONDED METAL PLANES A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on th... | 11/18/2010 |
| 20100283089 | METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first s... | 11/11/2010 |
| 20100281447 | METHOD FOR DETECTING CONTRADICTORY TIMING CONSTRAINT CONFLICTS The present invention discloses a method and apparatus for detecting timing constraint conflicts, the method comprising: receiving a timing constraint file; taking all test points in the timing constraint file as nodes, determining directed edges between the nodes and w... | 11/04/2010 |
| 20100277210 | THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchro... | 11/04/2010 |
| 20100269083 | Method of Employing Slew Dependent Pin Capacitances to Capture Interconnect Parasitics During Timing Abstraction of VLSI Circuits A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary ... | 10/21/2010 |
| 20100265778 | SEMICONDUCTOR MEMORY DEVICE A Static Random Access Memory (SRAM) includes word lines WL, bit lines BL, address decoders that select one of the word lines WL in response to an address signal AD, a sense amplifier that is activated in response to a sense amplifier enable signal SAE, and a sense ampl... | 10/21/2010 |
| 20100261318 | 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductiv... | 10/14/2010 |
| 20100258904 | BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer t... | 10/14/2010 |
| 20100255428 | METHOD TO MITIGATE RESIST PATTERN CRITICAL DIMENSION VARIATION IN A DOUBLE-EXPOSURE PROCESS A method to mitigate resist pattern critical dimension (CD) variation in a double-exposure process generally includes forming a photoresist layer over a substrate; exposing the photoresist layer to a first radiation; developing the photoresist layer to form a first patt... | 10/07/2010 |
| 20100244206 | METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A hi... | 09/30/2010 |
| 20100244198 | CMOS SIGE CHANNEL PFET AND SI CHANNEL NFET DEVICES WITH MINIMAL STI RECESS Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.... | 09/30/2010 |
| 20100213523 | eDRAM MEMORY CELL STRUCTURE AND METHOD OF FABRICATING A deep trench structure process for forming a deep trench in a silicon on insulator (SOI) substrate. The SOI substrate has a bulk silicon layer, a buried oxide (BOX) layer and an SOI layer. In the process, the trench fill is recessed only to a level within the SOI layer... | 08/26/2010 |
| 20100213522 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE TO REMEDY BOX UNDERCUT AND STRUCTURE FORMED THEREBY A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes form... | 08/26/2010 |
| 20100211922 | Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statisti... | 08/19/2010 |
| 20100210098 | SELF-ALIGNED CONTACT A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, fillin... | 08/19/2010 |
| 20100207246 | METHOD OF MAKING AN MIM CAPACITOR AND MIM CAPACITOR STRUCTURE FORMED THEREBY A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the s... | 08/19/2010 |
| 20100207245 | HIGHLY SCALABLE TRENCH CAPACITOR An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of... | 08/19/2010 |
| 20100207213 | BODY CONTACTS FOR FET IN SOI SRAM ARRAY Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not... | 08/19/2010 |
| 20100204940 | METHOD AND SYSTEM OF COMMONALITY ANALYSIS FOR LOTS WITH SCRAPPED WAFER According to an embodiment of the present invention is to provide methods to evaluate the impact of scrapped wafers on the remaining wafers in a lot by using scrap codes and statistical models. An embodiment of the present invention provides a method to obtain a baselin... | 08/12/2010 |
| 20100204839 | METHOD AND APPARATUS FOR THE MONITORING OF WATER USAGE WITH PATTERN RECOGNITION A method for monitoring water usage in a home or business through the use of pattern recognition. Wherein the system monitors water flow through a valve and monitors usage over a period of time to determine normal usage. Once a normal pattern of usage is determined the ... | 08/12/2010 |
| 20100203717 | CUT FIRST METHODOLOGY FOR DOUBLE EXPOSURE DOUBLE ETCH INTEGRATION A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines.... | 08/12/2010 |
| 20100201390 | PROBE CARD, METHOD FOR MANUFACTURING PROBE CARD, AND PROBER APPARATUS Embodiments of the present invention provide a probe card in which the positional shift of the tip of a probe can be compensated for in response to a change in the temperature, and a wafer test in a wide range of temperatures can be performed. More specifically, the pro... | 08/12/2010 |
| 20100201376 | DETECTING ASYMMETRICAL TRANSISTOR LEAKAGE DEFECTS A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifesting themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creat... | 08/12/2010 |
| 20100200960 | DEEP TRENCH CRACKSTOPS UNDER CONTACTS Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under ... | 08/12/2010 |
