Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Application No. | Application Title | Issue Date |
| 20110016326 | Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input ... | 01/20/2011 |
| 20100315894 | Low Power Sensing In a Multi-Port Sram Using Pre-Discharged Bit Lines A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage ... | 12/16/2010 |
| 20100309740 | Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being access... | 12/09/2010 |
| 20100269085 | Automated Generation of Oxide Pillar Slot Shapes in Silicon-On-Insulator Formation Technology A method of automated generation of oxide pillar (PX) slot shapes of a PX layer within silicon-on-insulator (SOI) structures that includes generating a placement grid on recess oxide (RX) shapes, creating PX placement markers on the placement grid along a perimeter of t... | 10/21/2010 |
| 20100230772 | ARRAY OF ALPHA PARTICLE SENSORS An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiatio... | 09/16/2010 |
| 20100230732 | FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portio... | 09/16/2010 |
| 20100157698 | CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier st... | 06/24/2010 |
| 20100117122 | Optimized Device Isolation A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath... | 05/13/2010 |
| 20100083496 | COMPLIANT MEMBRANE THIN FILM INTERPOSER PROBE FOR INTEGRATED CIRCUIT DEVICE TESTING A method for fabricating a compliant membrane probe for communication with an integrated circuit includes installing an array of conductive structures within a flexible membrane, the conductors comprising a beam structure having a first end and a second end, with each o... | 04/08/2010 |
| 20100080042 | INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of th... | 04/01/2010 |
| 20100049779 | SHARED PARALLEL ADDER TREE FOR EXECUTING MULTIPLE DIFFERENT POPULATION COUNT OPERATIONS A shared parallel adder tree for executing multiple different population count operations on a single datum includes a number of carry-save adders (CSAs) and/or half adders (HAs), arranged in rows, where certain CSAs and HAs are dedicated to a single population count op... | 02/25/2010 |
| 20100043858 | POWER GENERATION SYSTEM FOR AN ELECTRONIC SYSTEM An electronic system includes an electronic system cabinet housing at least one electronic system component and a power generation system. The power generation system includes a cooling system having a cooling medium that generates a cooling energy. The power generation... | 02/25/2010 |
| 20100014373 | REGULATING ELECTRICAL FUSE PROGRAMMING CURRENT An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second cur... | 01/21/2010 |
| 20100011278 | Soft Error Correction in Sleeping Processors An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft error... | 01/14/2010 |
| 20090327182 | CALENDAR BASED PERSONALIZED RECOMMENDATIONS A method providing intelligent suggestions and recommendations for wearable attire and digital program recording, includes: receiving information for a user's apparel and accessory purchases; parsing the received information for storage in a database to form an inventor... | 12/31/2009 |
| 20090310267 | METHOD, DESIGN STRUCTURES, AND SYSTEMS FOR CURRENT MODE LOGIC (CML) DIFFERENTIAL DRIVER ESD PROTECTION CIRCUITRY A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing ... | 12/17/2009 |
| 20090303821 | Apparatus and Method for Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being access... | 12/10/2009 |
| 20090303820 | APPARATUS AND METHOD FOR LOW POWER SENSING IN A MULTI-PORT SRAM USING PRE-DISCHARGED BIT LINES A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage ... | 12/10/2009 |
| 20090276644 | STRUCTURE FOR SEMICONDUCTOR POWER DISTRIBUTION AND CONTROL A design structure for dynamic integrated circuit power distribution and control is disclosed. The design structure includes an external power consumption target generator configured to generate a power dissipation target for one or more integrated circuits. The design ... | 11/05/2009 |
| 20090273968 | METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATION FOR PCRAM DEVICES A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line associated with a selected phase change element (PCE) to be read; comparing a first voltage on a node of the bit line with a second voltage on a delay... | 11/05/2009 |
| 20090273239 | SEMICONDUCTOR POWER DISTRIBUTION AND CONTROL SYSTEMS AND METHODS A system for dynamic integrated circuit power distribution and control is disclosed. The system includes an external power consumption target generator configured to generate a power dissipation target for one or more integrated circuits. The system also includes a firs... | 11/05/2009 |
| 20090268359 | ELECTROSTATIC DISCHARGE POWER CLAMP WITH IMPROVED ELECTRICAL OVERSTRESS ROBUSTNESS An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) and electrical overstress (EOS) events includes a resistor/capacitor (RC) triggering device configured between a pair of power rails; a silicon controlled rectifier (SCR) triggered by t... | 10/29/2009 |
| 20090257514 | SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side... | 10/15/2009 |
| 20090251474 | VIRTUAL COMPUTING AND DISPLAY SYSTEM AND METHOD A virtual computing and display system and method. The system includes a plurality of microprocessor-based devices which run software applications, and each microprocessor-based device generates at least one graphic processing unit command stream including a packet of g... | 10/08/2009 |
| 20090248778 | SYSTEMS AND METHODS FOR A COMBINED MATRIX-VECTOR AND MATRIX TRANSPOSE VECTOR MULTIPLY FOR A BLOCK-SPARSE MATRIX Systems and methods for combined matrix-vector and matrix-transpose vector multiply for block sparse matrices. Exemplary embodiments include a method of updating a simulation of physical objects in an interactive computer, including generating a set of representations o... | 10/01/2009 |
| 20090245110 | SYSTEM AND METHOD FOR IMPROVING EQUALIZATION IN A HIGH SPEED SERDES ENVIRONMENT A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side... | 10/01/2009 |
| 20090244954 | STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical comple... | 10/01/2009 |
| 20090241124 | ONLINE MULTIPROCESSOR SYSTEM RELIABILITY DEFECT TESTING A multiprocessor system comprising a plurality of processors is disclosed. The plurality of processors includes a first processor including first monitor on-chip and a second processor including a including a second monitor on-chip. The first monitor on-chip is configur... | 09/24/2009 |
| 20090235171 | APPARATUS AND METHOD FOR IMPLEMENTING WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARRAYS An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configur... | 09/17/2009 |
| 20090234633 | SYSTEMS AND METHODS FOR ENABLING INTER-LANGUAGE COMMUNICATIONS A method of enabling communication between a first person and a second person is disclosed. The method includes receiving at a server a message from the first person, the message addressed to the second person constructed in a first language; determining a preferred lan... | 09/17/2009 |
| 20090226084 | ADAPTIVE LOSSLESS DATA COMPRESSION METHOD FOR COMPRESSION OF COLOR IMAGE DATA An adaptive lossless data compression method for compression of color image data in a data processing system. The method includes comparing a plurality of components of a plurality of adjacent pixels in a digital image, calculating spatial differences between the plural... | 09/10/2009 |
| 20090219752 | Apparatus and Method for Improving Storage Latch Susceptibility to Single Event Upsets An apparatus for improving storage latch susceptibility to single event upsets includes a dual interconnected storage cell (DICE) configured within a storage latch circuit; a pair of separate three-state circuits configured to write the DICE latch, with each three-state... | 09/03/2009 |
| 20090219749 | METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SENSING OPERATION FOR RESISTIVE MEMORY DEVICES An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a programmable resistive memory element, the clamping device configured to clamp a fi... | 09/03/2009 |
| 20090219508 | SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGREATED DEVICES A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photovoltage difference between a scan probe device and a surface portion of an integrated device, the scan probe device being configured ... | 09/03/2009 |
| 20090207650 | SYSTEM AND METHOD FOR INTEGRATING DYNAMIC LEAKAGE REDUCTION WITH WRITE-ASSISTED SRAM ARCHITECTURE A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a re... | 08/20/2009 |
| 20090193283 | DESIGN STRUCTURE FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS A design structure embodied in a machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid cont... | 07/30/2009 |
| 20090193281 | APPARATUS AND METHOD FOR IMPLEMENTING SPECULATIVE CLOCK GATING OF DIGITAL LOGIC CIRCUITS A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control ... | 07/30/2009 |
| 20090189620 | COMPLIANT MEMBRANE PROBE A probe test head for a high density pin count integrated circuit, includes: a flexible membrane; an array of conductive structures, each one of the structures including a mechanically compliant probe tip affixed to the membrane, such that an attachment point enables me... | 07/30/2009 |
| 20090160689 | HIGH SPEED RESISTOR-BASED DIGITAL-TO-ANALOG CONVERTER (DAC) ARCHITECTURE A digital to analog converter (DAC) system comprising, a first segment, wherein a segment comprises, a first path including an array of resistors connected in series between a first reference voltage node and a second reference voltage node, wherein the array is connect... | 06/25/2009 |
| 20090158092 | SYSTEM AND METHOD FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply ha... | 06/18/2009 |
