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"That the automobile has practically reached the limit of its development is suggested by the fact that during the past year no improvements of a radical nature have been introduced."
Scientific American ; Jan. 2 edition, 1909
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| Number | Title | Issue Date |
| 8185952 | Static and dynamic firewalls A system comprising control logic adapted to activate multiple security levels for the system. The system further comprises a storage coupled to the control logic and comprising a stack, the stack associated with one, but not all, of the multiple security levels. Th... | 05/22/2012 |
| 8185790 | Resynchronization memory in series/parallel with control/output data scan cells An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data ... | 05/22/2012 |
| 8185789 | Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay t... | 05/22/2012 |
| 8185774 | Timer for low-power and high-resolution with low bits derived from set of phase shifted clock signals The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing most significant bits of a count. A clock signal generating stage provides a first set of phase shifted clock signals having m ... | 05/22/2012 |
| 8185672 | Transmission of data bursts on a constant data rate channel A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame struct... | 05/22/2012 |
| 8185666 | Compare instruction A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for d... | 05/22/2012 |
| 8184579 | ACK/NAK repetition schemes in wireless networks ACK/NAK repetition may be necessary to provide sufficient coverage for cell edge UEs. For a coverage limited UE, a NodeB may inform the UE that ACK/NAK repetition is needed. Such information can be explicitly signaled to the UE via DL control channels or conveyed th... | 05/22/2012 |
| 8184474 | Asymmetric SRAM cell with split transistors on the strong side An integrated circuit containing an SRAM cell array in which each SRAM cell includes an auxiliary NMOS driver or PMOS load transistor plus a bit-side passgate transistor and a bit-bar-side passgate transistor. An integrated circuit containing an SRAM cell array in w... | 05/22/2012 |
| 8184154 | Video surveillance correlating detected moving objects and RF signals A surveillance method periodically detects an image of the area, identifies and tracks each moving object in a succession of the detected images, detects radio frequency emissions from the area and correlates an identified object with a detected radio frequency emis... | 05/22/2012 |
| 8183939 | Ring oscillator A ring oscillator has at least one latch connected to the outputs of at least one oscillator stage, where the latch drives the outputs of the oscillator stage to opposite states during startup, and drive strength reduction circuitry to reduce drive strength of the l... | 05/22/2012 |
| 8183621 | Non-volatile memory cell having a heating element and a substrate-based control gate The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The progr... | 05/22/2012 |
| 8183137 | Use of dopants to provide low defect gate full silicidation The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the la... | 05/22/2012 |
| 8183117 | Device layout in integrated circuits to reduce stress from embedded silicon-germanium An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-... | 05/22/2012 |
| 8181067 | Apparatus and method for test and debug of a processor/core having advanced power management An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores... | 05/15/2012 |
| 8180635 | Weighted sequential variance adaptation with prior knowledge for noise robust speech recognition A method for adapting acoustic models used for automatic speech recognition is provided. The method includes estimating noise in a portion of a speech signal, determining a first estimated variance scaling vector using an estimated 2-order polynomial and the noise e... | 05/15/2012 |
| 8179812 | System and method for providing status reports of transmitted data packets in a data communications system A digital communications system for delivering data blocks includes at least one transmit/receive unit (TRU). The TRU includes a storage element for receiving transmit data packets and retransmit data packets from a sending unit and a processing element communicativ... | 05/15/2012 |
| 8179810 | Low-complexity primary synchronization sequences Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter is for use with a base station in a in a cellular communication system and includes a scheduling unit co... | 05/15/2012 |
| 8179775 | Precoding matrix feedback processes, circuits and systems An electronic device includes a first circuit (111) operable to generate a precoding matrix index (PMI) vector associated with a plurality of configured subbands, and further operable to form a compressed PMI vector from the PMI vector wherein the compressed ... | 05/15/2012 |
| 8179715 | 8T SRAM cell with four load transistors An integrated circuit containing SRAM cells with auxiliary load transistors on each data node. The integrated circuit also contains circuitry so that auxiliary load transistors in addressed SRAM cells may be biased independently of half-addressed cells. A process of... | 05/15/2012 |
| 8179446 | Video stabilization and reduction of rolling shutter distortion A method of processing a digital video sequence is provided that includes estimating compensated motion parameters and compensated distortion parameters (compensated M/D parameters) of a compensated motion/distortion (M/D) affine transformation for a block of pixels... | 05/15/2012 |
| 8179235 | Tactile interface for mobile devices A tactile input to a system having a speaker located in an enclosure with an audio port can be detected by generating a sound wave in response to a signal and sensing the phase relationship between the current phase and the voltage phase of the signal. While the aud... | 05/15/2012 |
| 8179198 | Variable gain amplifier having automatic power consumption optimization A variable gain amplifier may include a master amplifier that may be configured to generate a first current and a diode coupled with the master amplifier so that the first current passes through the diode which, when the first current is passing through the diode, g... | 05/15/2012 |
| 8179160 | Input-output (I/O) circuit supporting multiple I/O logic-level swings An integrated circuit (IC) includes an input/output (I/O) circuit supporting high-speed operation and multiple I/O logic-level swings. The I/O circuit includes a first output signal chain to generate outputs with a first logic level swing, and a second output signal... | 05/15/2012 |
| 8178976 | IC device having low resistance TSV comprising ground connection A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip h... | 05/15/2012 |
| 8178915 | Unitary floating-gate electrode with both N-type and P-type gates An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-... | 05/15/2012 |
| 8176460 | Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of th... | 05/08/2012 |
| 8176443 | Layout of printable assist features to aid transistor control Exemplary embodiments provide a method for laying out an IC design and the IC design layout. The IC design layout can include one or more gate features placed on an active region including a first pitch (p1) between any two adjacent gate features. Additionall... | 05/08/2012 |
| 8176374 | Data register control of TDI/AX1 to the data register The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary... | 05/08/2012 |
| 8176368 | Error correcting DPCM transcoding A digital system is provided that converts compressed data using an indexed transcoding lookup table. A stream of compressed data samples has data samples that represent one of n values corresponding to the first compression format. The transcoding table has at leas... | 05/08/2012 |
| 8176297 | Adaptive fetch advance control for a low power processor A digital signal processor (DSP) includes an instruction buffer queue (IBQ) with multiple lines, as well as a modifiable fetch advance parameter to specify a fetch advance setting for the IBQ. The DSP also has a control flow module. In response to execution of a pro... | 05/08/2012 |
| 8176241 | System and method for optimizing DRAM refreshes in a multi-channel memory controller In accordance with the teachings of the present invention, a system and method for optimizing DRAM refreshes in a multi-channel memory controller are provided. In a particular embodiment, the method includes receiving, at a router in a light modulation system, a sig... | 05/08/2012 |
| 8175584 | System and method to facilitate downloading data at a mobile wireless device The invention relates to systems and method to facilitate downloading a data file. In one embodiment, a method includes receiving at a first wireless communication device a request to download a requested data file. A determination is made at the first wireless comm... | 05/08/2012 |
| 8175549 | Closed loop transmitter IQ calibration A novel and useful apparatus for and method of closed loop IQ calibration for use in a transmitter. The IQ calibration mechanism functions to provide calibration of IQ imbalance in the presence of real world RF impairments. An iterative process is used to update the... | 05/08/2012 |
| 8175375 | Method of compression of video telephony images A method of compression of videotelephony images characterized by: creating (10) a learning base containing images; centering the learning base about zero; determining component images by principal component analysis (12); and keeping a number of signi... | 05/08/2012 |
| 8175147 | Video coding rate control Video encoding (such as H.263, MPEG-4, H.264/AVC) modifies TMN5-type rate control frame skipping and quantization parameter updating according to buffer fullness levels with I-frame initial quantization parameter values depend upon quantization parameter value of pr... | 05/08/2012 |
| 8175077 | Mapping schemes for secondary synchronization signal scrambling Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary s... | 05/08/2012 |
| 8175021 | Method for transmission of unicast control in broadcast/multicast transmission time intervals Embodiments of the invention provide methods for maximizing the bandwidth utilization in the uplink of a communication system supporting time division multiplexing between unicast and multicast/broadcast communication modes during transmission time intervals in the ... | 05/08/2012 |
| 8174955 | Random access preamble coding for initiation of wireless mobile communications sessions A wireless communications network, including a base station (10) and wireless units (UE), is disclosed. The wireless units (UE) request a connection with the base station (10) by the transmission of a preamble within time slots designated by the base s... | 05/08/2012 |
| 8174953 | Input current channel device An input current channel device is described. This device comprises a first terminal for receiving a reference signal; a second terminal for receiving a first target signal; a pass through device coupled to the first terminal, the pass through device operative for t... | 05/08/2012 |
| 8174914 | Method and structure for SRAM Vmin/Vmax measurement A parametric test circuit is disclosed (FIG. 8B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (... | 05/08/2012 |
