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| Number | Title | Issue Date |
| 7463056 | Writeable shift register lookup table in FPGA with SRAM memory cells in lookup table reprogrammed by writing after initial configuration An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a... | 12/09/2008 |
| 7464350 | Method of and circuit for verifying a layout of an integrated circuit device A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated circuit device; generating an implant table file having data showing a r... | 12/09/2008 |
| 7460848 | Differential signal strength detector A signal detection circuit includes a first signal multiplier operably coupled to square an input signal, a second signal multiplier operably coupled to square a reference signal, and a filter module operably coupled to produce a digital output representative of the... | 12/02/2008 |
| 7461193 | Network media access controller embedded in a programmable logic device—receive-side client interface A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. ... | 12/02/2008 |
| 7460586 | Selective signal coupling in high speed I/O circuits According to an example embodiment, a data-transfer circuit transfers high-speed input data toward an output port by coupling the data circuit selectively through a resistive-impedance circuit and a capacitive-impedance circuit to accommodate both high-frequency and... | 12/02/2008 |
| 7456654 | Method and apparatus for a programmable level translator A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages... | 11/25/2008 |
| 7454556 | Method to program non-JTAG attached devices or memories using a PLD and its associated JTAG interface A method is provided to program a memory device through a JTAG interface of an attached component with programmable logic, wherein the memory device does not have a JTAG interface. Initially, programming hardware to provide for programming of the attached memory is ... | 11/18/2008 |
| 7454546 | Architecture for dynamically reprogrammable arbitration using memory An architecture for a Block RAM (BRAM) based arbiter is provided to enable a programmable logic device (PLD) to efficiently form a memory controller, or other device requiring arbitration. The PLD arbiter provides low latency with a high clock frequency, even when i... | 11/18/2008 |
| 7453311 | Method and apparatus for compensating for process variations A method and apparatus compensate for process variations in the fabrication of semiconductor devices. A semiconductor device includes a control circuit that measures a performance parameter of the device, and in response thereto selectively biases one or more well r... | 11/18/2008 |
| 7453301 | Method of and circuit for phase shifting a clock signal The methods and circuits of the various embodiments of the present invention relate to phase shifting of a generated clock signal. According to one embodiment, a method of phase shifting a clock signal using a delay line is described. The method comprises the steps ... | 11/18/2008 |
| 7453286 | Comparator and method of implementing a comparator in a device having programmable logic A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output a... | 11/18/2008 |
| 7453273 | Method and apparatus for analyzing current in an integrated circuit under test Method and apparatus for analyzing current in an integrated circuit under test is described. In one example, an image from detected photon emissions from the integrated circuit is generated. A first intensity of the photon emissions at a first region in the image in... | 11/18/2008 |
| 7453261 | Method of and system for monitoring the functionality of a wafer probe site A method of monitoring the functionality of a wafer probe is disclosed. The method comprises applying a multi-site probe to a plurality of semiconductor dies; comparing the failure rate of a first probe site of the multi-site probe with the failure rate of a second ... | 11/18/2008 |
| 7452765 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening se... | 11/18/2008 |
| 7453297 | Method of and circuit for deskewing clock signals in an integrated circuit The methods and circuits of the various embodiments of the present invention relate to deskewing a generated clock signal. According to one embodiment, a method of deskewing a clock signal in a circuit having a delay line comprises steps of measuring an intrinsic de... | 11/18/2008 |
| 7454675 | Testing of a programmable device A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element... | 11/18/2008 |
| 7454658 | In-system signal analysis using a programmable logic device Method for in-system signal analysis is described. A programmable logic device is coupled within a signal communications system. A signal processing core is instantiated in programmable logic of the programmable logic device. At least one communication signal is pro... | 11/18/2008 |
| 7454587 | Method and apparatus for memory management in an integrated circuit Method and apparatus for managing memory logic is described. In one example, user logic, virtual port logic, and a processor are provided. The user logic is configured to provide allocation requests for the memory logic, access requests for the memory logic, and de-... | 11/18/2008 |
| 7451420 | Determining reachable pins of a network of a programmable logic device A processor-implemented method is provided for determining reachable pins functionally connected to a network of a netlist that describes a programmable logic device (PLD) design. A netlist and an identification of the network in the netlist are input. Characterizat... | 11/11/2008 |
| 7451417 | Timing annotation accuracy through the use of static timing analysis tools A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updati... | 11/11/2008 |
| 7451369 | Scalable columnar boundary scan architecture for integrated circuits An integrated circuit having a scalable boundary scan architecture. Logic elements, each including at least one data storage element, are arranged in rows and columns. A data distribution system couples the data storage elements together to form a boundary scan chai... | 11/11/2008 |
| 7451425 | Determining controlling pins for a tile module of a programmable logic device A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile module are input. Characterization data is input for a sub-module of the ... | 11/11/2008 |
| 7451424 | Determining programmable connections through a switchbox of a programmable logic device A processor-implemented method is provided for determining programmable connections through a switchbox module of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of the switchbox module are input. Characterizat... | 11/11/2008 |
| 7451423 | Determining indices of configuration memory cell modules of a programmable logic device A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell ... | 11/11/2008 |
| 7451422 | Simultaneous assignment of select I/O objects and clock I/O objects to banks using integer linear programming A method of assigning I/O objects to banks of a target device can include concurrently assigning I/O objects, including select I/O objects and clock I/O objects, of the circuit design to I/O groups according to an I/O standard associated with each I/O object. Each I... | 11/11/2008 |
| 7450431 | PMOS three-terminal non-volatile memory element and method of programming A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate di... | 11/11/2008 |
| 7451421 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second ... | 11/11/2008 |
| 7444603 | Transformation of graphs representing an electronic design in a high modeling system Methods and apparatus are provided for processing an electronic design in a high level modeling system. A first graph is generated, with the nodes representing basic elements of the electronic design and including a shared node representing the basic element of a bl... | 10/28/2008 |
| 7444349 | Control of concurrent access to a partitioned data file Method and apparatus for controlling concurrent access to a data file. The data file is organized into a plurality of partitions, and a lock file that is accessible to the client applications is persistently stored. The lock file includes lock objects that correspon... | 10/28/2008 |
| 7444610 | Visualizing hardware cost in high level modeling systems Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the cir... | 10/28/2008 |
| 7440530 | Circuit for and method of optimizing the transmission of data on a communication channel A circuit for optimizing the transmission of data on a communication channel is disclosed. According to one embodiment of the invention, a circuit comprises a transmitter circuit having a programmable output characteristic and being coupled to a transmission media. ... | 10/21/2008 |
| 7440495 | FPGA having AC coupling on I/O pins with an effective bypass of the AC coupling DC balance is obtained in an integrated circuit (IC) having I/O pins with AC coupling by effectively bypassing the AC coupling. The DC balance is accomplished by mixing in a known, low frequency mix signal or carrier in a circuit external to the IC and then digitall... | 10/21/2008 |
| 7440454 | Packet reshuffler and method of implementing same A packet reshuffler and a method of implementing the same is described. In one example, a digital logic circuit in a transmitter for sending packets stored in a set of buffers includes circular shift register logic, encoder logic, selection logic, and combinatorial ... | 10/21/2008 |
| 7439763 | Scalable shared network memory switch for an FPGA A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based o... | 10/21/2008 |
| 7437701 | Simulation of a programming language specification of a circuit design Various approaches for simulating a circuit design are disclosed. In one approach, a first specification of a testbench and a second specification of the circuit design are generated in a hardware description language. The circuit design is synchronous to at least o... | 10/14/2008 |
| 7437695 | Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical po... | 10/14/2008 |
| 7437633 | Duty cycle characterization and adjustment Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a fir... | 10/14/2008 |
| 7437582 | Power control in a data flow processing architecture Method and system for dynamically adjusting performance of circuitry blocks are described. A first circuit domain is coupled to an interim storage device. The first circuit domain includes a first level shifter coupled to an input of a first circuitry block and a se... | 10/14/2008 |
| 7437280 | Hardware-based co-simulation on a PLD having an embedded processor Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-b... | 10/14/2008 |
| 7436726 | Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write addres... | 10/14/2008 |
