Assignee: Xilinx, Inc.

Location: San jose, CA
No. of patents: 1077

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Number	Title	Issue Date
8448122	Implementing sub-circuits with predictable behavior within a circuit design A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit ...	05/21/2013
8447957	Coprocessor interface architecture and methods of operating the same A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The proce...	05/21/2013
8447581	Generating simulation code from a specification of a circuit design During the elaboration and synthesis of a circuit design, a parse tree generally must be fully expanded to access memory resources and data of individual module instances in order to perform optimizations that will result in better runtime performance of generated s...	05/21/2013
8446195	Strobe signal management to clock data into a system A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the s...	05/21/2013
8446169	Impedance tuning for termination An embodiment of an impedance adjustment apparatus is disclosed. For this embodiment of an impedance adjustment apparatus, a differential driver circuit has an input port, a first output port, a second output port, a first bias node, and a second bias node. A first ...	05/21/2013
8443344	Methods for identifying gating opportunities from a high-level language program and generating a hardware definition Approaches for generating a hardware definition from a program specified in a high-level language. In one approach, a first set of blocks of instructions in the high-level language program is identified. Each block in the first set is bounded by a respective loop de...	05/14/2013
8443256	Method and apparatus for determining a cyclic redundancy check (CRC) for a data message A method of creatine a CRC (Cyclic Redundancy Check) code for a data message in a data communications system includes sequentially placing portions of the data message on a bus of width W bits consisting of an integral number N of segments of width S. An initial por...	05/14/2013
8443230	Methods and systems with transaction-level lockstep Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution ...	05/14/2013
8443129	Method and apparatus for implementing a data bus interface A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data p...	05/14/2013
8443102	Pipeline of a packet processor programmed to extract packet fields A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies packet fields. The programmable compute pipeline includes a sequ...	05/14/2013
8443031	Systolic array for cholesky decomposition A systolic array for Cholesky decomposition of an N×N matrix is described. A plurality of processing cells, including a corner cell, N−1 boundary cells, and (N2−3N+2)/2 internal cells, are arranged into N−1 rows and N columns of processing cells. E...	05/14/2013
8442105	Equalization for minimum mean-square-error successive-interference-cancellation In an embodiment of an equalizer, a demodulator for MMSE-SIC receives a symbol vector to provide first information. A decoder receives the first information to provide second information to the demodulator. The decoder iteratively processes the first information to ...	05/14/2013
8441562	Color filter array alignment detection In one embodiment of the present invention, a method for determining a phase alignment of a Bayer color filter array is provided. A quincunx lattice of the color filter array corresponding to a first color component is determined from an input frame of image data. E...	05/14/2013
8441038	Nano relay with floating bridge A nano-electric switch includes a cavity base, a confinement wall, and a cavity top defining a cavity. A floating conductive bridge movable within the cavity completes an electrical circuit between a first electrical contact and a second electrical contact in a firs...	05/14/2013
8438436	Secure design-for-test scan chains A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling ...	05/07/2013
8438357	Method and apparatus for calculating number of memory access cycles when transferring data to or from a memory A technique applicable during the transfer of data to and from a memory involves: operating a memory interface using memory access cycles that each transfer a quantity of data D across the memory interface; receiving a request to transfer a quantity of data Q across...	05/07/2013
8438326	Scalable memory interface system A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controll...	05/07/2013
8436658	Method and apparatus for signaling characteristics of a transmitted signal A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal represents either a binary signal or a multi-valued signal to allow signaling of one or...	05/07/2013
8436642	Control of termination capacitance for maximum transmitter bandwidth extension An integrated circuit device includes an input/output (IO) pad, and a programmable termination capacitance circuit coupled to the IO pad, the programmable termination capacitance circuit comprising at least one compensation bank, wherein each of the at least one com...	05/07/2013
8429482	Multi-stage forward error correction decoding In one embodiment, a multi-stage decoder circuit is provided. Each stage of the decoder circuit is configured to perform one or more decoding iterations and produce an error mask indicating errors detected in the decoding stage. A compression circuit is coupled to o...	04/23/2013
8427266	Integrated circuit inductor having a patterned ground shield An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structur...	04/23/2013
8427193	Intellectual property core protection for integrated circuits A method of using an integrated circuit (IC) can include reading a device code from a selected IC, calculating a measure of randomness from a plurality of values specified within the device code, and comparing the measure of randomness to a randomness criterion. A d...	04/23/2013
8423935	Method and apparatus for verifying output-based clock gating One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the...	04/16/2013
8418221	Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devices Methods of prioritizing untested routing resources in programmable logic devices (PLDs) to generate test suites that include a minimal number of test designs. The untested routing resources are prioritized (e.g., placed into an ordered list) based on a number of unt...	04/09/2013
8418115	Routability based placement for multi-die integrated circuits A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of th...	04/09/2013
8418096	Methods for inhibiting reverse engineering of circuit designs Various methods for inhibiting reverse engineering of a circuit design are provided. In one embodiment, a circuit design is initially mapped to a plurality of identified hardware components of a target device using a first table that indicates a first set of logic p...	04/09/2013
8418095	Compilation and simulation of a circuit design One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each...	04/09/2013
8418006	Protecting a design for an integrated circuit using a unique identifier An embodiment of the invention relates to an integrated circuit that includes an identifier reader which may be, e.g., a physically unclonable function reader that generates a unique and reproducible identifier for the integrated circuit, and a related method. An er...	04/09/2013
8417965	Method and circuit for secure definition and integration of cores An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an ...	04/09/2013
8417867	Multichip module for communications An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the...	04/09/2013
8417758	Left and right matrix multiplication using a systolic array A method, machine-readable medium, and systolic array for left matrix multiplication of a first matrix and a second matrix are described. The first matrix is a triangular matrix, and a cross-diagonal transpose of the first matrix is loaded into a triangular array of...	04/09/2013
8417749	Specifying a multirate digital filter based on a ratio of an input sample rate to an output sample rate Approaches for preparing a design of a digital multirate filter. In one approach, an objective function and an input and output characteristic are input for determining an effectiveness of a plurality of filters. The characteristic includes an overall rate change va...	04/09/2013
8416950	Copy protection without non-volatile memory An integrated circuit includes a fingerprint element and a decryption circuit. The fingerprint element generates a fingerprint, where the fingerprint is reproducible and represents an inherent manufacturing process characteristic unique to the integrated circuit dev...	04/09/2013
8416841	Multiple-input multiple-output (MIMO) decoding with subcarrier grouping Multiple input multiple output (MIMO) receiver circuitry is described. In one circuit, input circuitry provides a matrix of unresolved symbols received from a plurality of receive antennas. Channel estimation circuitry constructs a plurality of channel matrices incl...	04/09/2013
8415976	Optimized interconnection networks A non-blocking routing network includes a plurality of external inputs and external outputs. Each row of a first plurality of routing rows provides a routing path from at least one of the external inputs to at least one of the external outputs and includes first thr...	04/09/2013
8415974	Methods and circuits enabling dynamic reconfiguration A method of enabling partial reconfiguration in a device having configurable resources is disclosed. The method comprises receiving a configuration bitstream comprising configuration bits; configuring the configurable resources of the device using the configuration ...	04/09/2013
8415783	Apparatus and methodology for testing stacked die A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface. ...	04/09/2013
8412497	Predicting simultaneous switching output noise of an integrated circuit Predicting simultaneous switching output noise of an IC device is described. User input is obtained. The user input includes: an identification of an input/output bank of an integrated circuit die; an identification of a device package substrate to which the integra...	04/02/2013
8411703	Method and apparatus for a reduced lane-lane skew, low-latency transmission system A method and apparatus for a multiple lane transmission system that provides a fixed, low-latency mode of operation with reduced lane-lane skew while process, voltage, and temperature (PVT) variation, as well as other sources of variation, occur over time. Multiplex...	04/02/2013
8410772	Bias circuit generating bias from supply and threshold voltages A bias circuit generates a bias voltage. The bias circuit includes a first, a second, and a third detection circuit and a summing circuit. The first detection circuit generates a first characterization voltage that represents a variation of a power supply voltage fr...	04/02/2013

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Assignee: Xilinx, Inc.