Assignee: Xilinx, Inc.

Location: San jose, CA
No. of patents: 853

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Number	Title	Issue Date
8185850	Method of implementing a circuit design using control and data path information A method of implementing a circuit design is described. The method comprises specifying criteria for control and data path identification; generating a representation for the circuit design; analyzing the representation based upon the criteria for control and data p...	05/22/2012
8185720	Processor block ASIC core for embedding in an integrated circuit A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar in...	05/22/2012
8185678	Method and apparatus for controlling a data bus A method and apparatus for controlling a data bus system is provided. A data bus system may use different hardware to perform transceiver and system control functions. The various embodiments of the invention increase compatibility of a data bus system with differen...	05/22/2012
8184696	Method and apparatus for an adaptive systolic array structure A method and apparatus for an adaptive systolic array structure is initially configured for motion estimation calculations and optionally reconfigured as the motion estimation algorithm progresses. A scheduling map of the processing element (PE) calculations for a g...	05/22/2012
8184029	Phase interpolator A phase interpolator is described. The phase interpolator can have a code-to-bias converter, and a phase interpolation interface. In an embodiment of a code-to-bias converter, a single digital-to-analog converter is provided to generate bias signaling associated wit...	05/22/2012
8183881	Configuration memory as buffer memory for an integrated circuit Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration m...	05/22/2012
8183105	Integrated circuit device with stress reduction layer An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a redu...	05/22/2012
8182141	Method and circuit for providing distributed temperature sensing in an integrated circuit In one embodiment, an integrated circuit for providing distributed temperature sensing is disclosed. For example, the integrated circuit comprises a plurality of circuit components, an internal temperature sensing device deployed among the plurality of circuit compo...	05/22/2012
8181149	Interface for managing multiple implementations of a functional block of a circuit design Approaches for assembling an electronic circuit design. A processor performs operations including instantiating and coupling a plurality of instances of functional blocks in the design, including at least one meta block instance. The plurality of instances of functi...	05/15/2012
8181140	T-coil network design for improved bandwidth and electrostatic discharge immunity A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon ...	05/15/2012
8180919	Integrated circuit and method of employing a processor in an integrated circuit According to various embodiments of the present invention, an intelligent framer/mapper integrates the framer, mapper, and the controlling function of the host processor, implemented as either a soft processor or an embedded processor, into a single device, such as ...	05/15/2012
8180820	Generation of a remainder from division of a first polynomial by a second polynomial Generating a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a ...	05/15/2012
8180616	Component tracing in a network packet processing device Approaches for gathering packet processing information. A directed graph is used to represent the packet processing system. In response to each network packet input to the system, an associated, unique packet identifier is established for the network packet. Each in...	05/15/2012
8179159	Configuration interface to stacked FPGA A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a fra...	05/15/2012
8178962	Semiconductor device package and methods of manufacturing the same A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals couple...	05/15/2012
8176461	Design-specific performance specification based on a yield for programmable integrated circuits A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and s...	05/08/2012
8176449	Inference of hardware components from logic patterns The present invention provides a simplified process for inference using a generic logic pattern corresponding to one or more generic functions provided by the hardware component. A circuit design is mapped into a plurality of interconnected hardware components, and ...	05/08/2012
8174112	Integrated circuit device with low capacitance and high thermal conductivity interface An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor...	05/08/2012
8166445	Estimating Icc current temperature scaling factor of an integrated circuit An embodiment of the present invention reduces resources needed to estimate the Icc Current Temperature Scaling Factor (ITSF) of a device, and provides a method and apparatus to estimate ITSF from the device speed and performance characteristics which can be measure...	04/24/2012
8166431	Reducing startup time of an embedded system that includes an integrated circuit A method of reducing startup time of an embedded system can include: instantiating a circuit, specified by a first circuit design, within an integrated circuit (IC), booting a first build of an operating system executed by a processor to a steady state, and responsi...	04/24/2012
8166366	Partial configuration of programmable circuitry with validation Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation,...	04/24/2012
8165845	Method and apparatus for statistical identification of devices based on parametric data A method and apparatus is provided for the calculation of maverick control limits. The maverick control limit method selects the correct parameter(s) as critical parameters to be utilized by the maverick control limit method. Next, the maverick control limit method ...	04/24/2012
8161436	Method and system for transforming fork-join blocks in a hardware description language (HDL) specification The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications i...	04/17/2012
8161365	Cyclic redundancy check generator A cyclic redundancy check (“CRC”) generator and method therefor are described. Checksum bits and checksum enable bits are bitwise ANDed to provide interim checksum outputs. The interim checksum outputs are XORed to provide resultant checksum outputs. Data bits a...	04/17/2012
8161249	Method and apparatus for multi-port arbitration using multiple time slots An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming...	04/17/2012
8161212	Data operations across parallel non-volatile input/output devices An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be c...	04/17/2012
8160092	Transforming a declarative description of a packet processor Methods are provided for transforming a declarative description of a processor of the packets of a communication protocol. A first declarative description of the packet processor is input. The first declarative description includes rules that include actions for man...	04/17/2012
8159301	Differential amplifier with hysteresis An amplifier circuit having a differential input and an amplifier output is provided. In some examples, the amplifier circuit includes a first input stage having a first complementary transistor pair providing a first input and a first output, the first input being ...	04/17/2012
8159263	Programmable integrated circuit with voltage domains A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a pl...	04/17/2012
8156459	Detecting differences between high level block diagram models A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive differences through traversal of the block hierarchy which is complex and ...	04/10/2012
8156456	Unified design methodology for multi-die integrated circuits A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. T...	04/10/2012
8155907	Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice...	04/10/2012
8155071	Cross-layer allocation of spectral resource to spatially multiplexed communication A system detects a communication transmitted from multiple transmitting antennas. The system includes a media access controller and a physical block. Based on a signal to noise ratio (SNR), the allocation circuit of the media access controller assigns a portion of a...	04/10/2012
8154989	Recovering a shared channel within a network from a deadlock state A method of processing data within a controller for a network can include identifying frames within a data stream within the network (1110) and detecting a deadlock state according to a number of consecutive frames comprising at least one set control bit (...	04/10/2012
8150638	Predicting parasitic capacitance in schematic circuit simulations using sub-circuit modeling A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a...	04/03/2012
8149612	Memory array and method of implementing a memory array A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the firs...	04/03/2012
8146045	High-level circuit architecture optimizer A method for optimizing a high-level circuit architecture for an integrated circuit is described. Descriptions of components of the circuit architecture and optimization goals for the components are received. At least one stopping criterion for the cost functions is...	03/27/2012
8146041	Latch based optimization during implementation of circuit designs for programmable logic devices A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed u...	03/27/2012
8146040	Method of evaluating an architecture for an integrated circuit device A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the in...	03/27/2012
8146036	Circuit for and method of determining a process corner for a CMOS device A circuit for determining a process corner for a CMOS device of an integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising an NMOS transistor and a PMOS transistor of the integrated circuit; reference circuit comprising elements f...	03/27/2012

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Assignee: Xilinx, Inc.