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| Number | Title | Issue Date |
| 6876031 | Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate ov... | 04/05/2005 |
| 7423642 | Efficient video frame capturing A method for capturing images includes associating the pixels with tiles. An input data sequence representing respective current values of the pixels of a currently-captured image frame is accepted. Within each of at least some of the tiles, the current values are c... | 09/09/2008 |
| 7398554 | Secure lock mechanism based on a lock word One or more lock words in a non-volatile memory with write ability correspond to lockable features of a protected system including the memory. A lockable feature should be locked when the corresponding lock word has a value equal to one of a limited number of predet... | 07/08/2008 |
| 7388358 | Method and apparatus for a pulse width modulated DC-DC converter A pulse width modulated pulse signal is generated and its duty cycle adjusted according to at least two different schedules, for example, a coarse tuning cycle and a fine tuning cycle. The target duty cycle is derived according to an offset between output voltage an... | 06/17/2008 |
| 7369441 | Sensing circuit for multi-level flash memory A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and maintaining a constant difference between two approximate reference voltages.... | 05/06/2008 |
| 7342388 | Low ripple line-state dependent PWM DCDC converter controllers and methods for SLIC switching load regulation Low ripple line-state dependent PWM DCDC converter controllers and methods for subscriber line interface circuit switching load regulation. In accordance with the method, line state is monitored to determine the target voltage for that state, and a DCDC converter is... | 03/11/2008 |
| 7329925 | Device for electrostatic discharge protection A device for electrostatic discharge (ESD) protection is disclosed. The device for electrostatic discharge protection includes a lateral bipolar transistor and a diode. The semiconductor transistor has an emitter, a base and a collector electrically connected to a f... | 02/12/2008 |
| 7313282 | Method and apparatus for digital signal processing The present invention is a method and an apparatus for digital signal processing. The method extracts a plurality of data which is not zero or repeated and recognizes a plurality of coordinate data corresponding to the extracted data. The method saves memory space a... | 12/25/2007 |
| 7301917 | Multi channels data transmission control method A multi channels data transmission control method comprises steps of: provide multiple channels and channel counters with the same number, these channels have multiple data frames; based on these channels and data frames to generate an acknowledgement record matrix;... | 11/27/2007 |
| 7286664 | Efficient implementation of MD5 message-digest algorithm (RFC1321) on an 8 bit micro-controller A method for implementing an MD5 algorithm on an 8-bit micro-controller includes providing a pointer to an entry in a table stored in a read only memory (ROM). The entry corresponds to an operation in the MD5 algorithm. The method also includes retrieving from the e... | 10/23/2007 |
| 7283964 | Method and apparatus for voice controlled devices with improved phrase storage, use, conversion, transfer, and recognition The embodiments of the invention provide for the storage of speech phrases. Speech phrases are processed by a speaker-independent speech recognition engine of a voice controlled device. This engine returns a speaker-independent representation of the phrase. The spea... | 10/16/2007 |
| 7265622 | Differential difference amplifier A differential difference amplifier includes a first pair of differential input terminals and a second pair of differential input terminals. The differential difference amplifier has a pair of differential output terminals to output a voltage in relation to a differ... | 09/04/2007 |
| 7260212 | Method and apparatus for subscriber line control circuit A subscriber line interface circuit apparatus includes a linefeed circuit and a subscriber line control circuit (SLCC). In an embodiment, the linefeed circuit includes a signal conversion circuit which provides a differential mode signal and a common mode signal in ... | 08/21/2007 |
| 7257103 | Wireless communication method with channel shared function The present invention is relative to a method for wireless communication with channel share function. There are a first T/R (Transmitting/Receiving) unit and a second T/R unit in a wireless communication channel. The method comprises steps of: transmitting a first d... | 08/14/2007 |
| 7221027 | Latchup prevention method for integrated circuits and device using the same An integrated circuit preventing latchup. In the integrated circuit, an internal circuit is disposed in a substrate and has a parasitic SCR structure. At least one ESD protection circuit and active area are disposed on the substrate and coupled to a pad. A first cur... | 05/22/2007 |
| 7219507 | Configurable, nonlinear fan control for system-optimized autonomous cooling Disclosed herein are methods and systems for controlling fan speed by approximating a nonlinear temperature control function activated within a given temperature control range. The temperature control range is divided into numerous linear segments each of which is a... | 05/22/2007 |
| 7197299 | Multiple message multilevel analog signal recording and playback system containing configurable analog processing functions A multilevel analog recording and playback system is described. The analog recording and playback system provides a variety of analog processing functions to enhance system level integration. The analog recording and playback system is an fully configurable integrat... | 03/27/2007 |
| 7186658 | Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combin... | 03/06/2007 |
| 7185139 | Easy access port structure and access method The present invention provides an easy access ports structure. In accordance with the present invention, each port has a register bank. Each register bank has the same address. A global register is used in the present invention to store the status values. When opera... | 02/27/2007 |
| 6940326 | Frequency signal enabling apparatus and method thereof The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pu... | 09/06/2005 |
| 6865186 | Multiple message multilevel analog signal recording and playback system having memory array configurable for analog and digital storage and serial communication A multilevel analog recording and playback system is described. An analog processing circuit processes analog data. A storage circuit includes a non-volatile memory array, a switching circuit, and a communication interface. The non-volatile memory array stores analo... | 03/08/2005 |
| 6798253 | Signal sorting device and method A current sorter has an input section, a comparing section, and a control section. The input section includes a first input unit and a second input unit and generate a first output signal that is indicative of the first input signal and a second output signal that i... | 09/28/2004 |
| 6718220 | Method and system of monitoring apparatuses of manufacturing IC A method and system of monitoring apparatuses of manufacturing integrated circuit (IC) detects the problems during wafers processing by replaying the apparatus events. First, the method and system download the data of apparatus events, and then calculate the achieve... | 04/06/2004 |
| 6674325 | Balanced current converter with multiple pulse width modulated channels A balanced current converter with multiple PWM converter channels has an error amplifier, a main converter channel and at least one parallel converter channel. The converter provides a DC power output and feeds back an average output voltage signal. The e... | 01/06/2004 |
| 6667201 | Method for manufacturing flash memory cell The present invention discloses a method for manufacturing a flash memory cell having a horizontal surrounding gate (HSG). The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell ... | 12/23/2003 |
| 6602735 | Method of fabricating a semiconductor chip package with a lead frame and multiple integrated circuit chips A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection lead... | 08/05/2003 |
| 6541325 | Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so t... | 04/01/2003 |
| 6457094 | Memory array architecture supporting block write operation A memory array architecture that supports block write operation and has many advantages over conventional memory array architectures. A memory array is partitioned into a number of (N) segments. Each segment includes at least one bit line. Each segment is... | 09/24/2002 |
| 6452843 | Method and apparatus for testing high-speed circuits based on slow-speed signals Techniques and circuits for testing high-speed circuits using slow-speed input signals. Various designs for a "stimulus" generator are provided, which is capable of generating a high-speed stimulus based on, or in response to, one or more input signals. I... | 09/17/2002 |
| 6424183 | Current comparator The present invention discloses a current comparator having simple, cheap and fast characteristics, especially discloses a current comparator having a small dead zone and excellent driving capability. The current comparator of the present invention compri... | 07/23/2002 |
| 5659700 | Apparatus and method for generating a modulo address A method and apparatus for generating a modulo address for accessing a circular buffer. The method and apparatus accept as inputs a length L of the circular buffer, a current address A of the circular buffer, and an offset M between the current address an... | 08/19/1997 |
