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| Number | Title | Issue Date |
| 7336521 | Memory pumping circuit A memory pumping circuit is proposed. The feature of the present invention is the charging capacitor of the pumping circuit is a DRAM cell for enhancing the capacitance. ... | 02/26/2008 |
| 7313729 | Low-cost debugging system with a ROM or RAM emulator A low-cost micro-controller debugging system with a ROM or RAM emulator is disclosed. The system includes a target microcontroller (MCU) and at least one ROM connected together, with a debugger unit which debugs that target MCU. A ROM/RAM emulator is connected to th... | 12/25/2007 |
| 7256461 | Electrostatic discharge (ESD) protection device The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance... | 08/14/2007 |
| 7161505 | A/D converter with comparators and low-power detection mode for resistive matrix keyboards An apparatus and method is disclosed for providing a fast, low power consumption, detection of at least one depressed key in a resistive matrix keyboard. The common contact of each row of a resistive matrix is connected to a first input of each of a plurality of ana... | 01/09/2007 |
| 7137096 | Interconnect structure of a chip and a configuration method thereof A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power... | 11/14/2006 |
| 7129600 | Control circuit with multiple power sources The present invention provides a control circuit with multiple power sources, which accepts an output signal from a comparator circuit. This control circuit with multiple power sources contains two components: one is a voltage transferring circuit, which connects to... | 10/31/2006 |
| 7073094 | Method and systems for programming and testing an embedded system An embedded system comprising an embedded core, a non-volatile memory (e.g., a Flash memory or a ROM), and a volatile memory (e.g., RAM). The embedded core performs processing tasks for the embedded system. The non-volatile memory stores executable codes for the emb... | 07/04/2006 |
| 7046594 | Apparatus and method for optical storage system focus control A method of adjusting the focus control for an optical storage system where light is reflected from a surface towards a lens. The method includes receiving a reflected light in the form of a spot, dividing the spot into a plurality of areas, generating an adjustment... | 05/16/2006 |
| 7002332 | Source and sink voltage regulator A source and sink voltage regulator includes an output circuit, an amplifier circuit and a bias current control circuit. The output circuit is used to output a loading current under a stable output voltage and is further used to draw a reverse loading current while ... | 02/21/2006 |
| 6977532 | Dual differential comparator circuit with full range of input swing The differential comparator circuit for receiving an input voltage within a pre-determined range, amplifying the input voltage, and outputting an output voltage is provided. The circuit includes: a first differential comparator for receiving the input voltage within... | 12/20/2005 |
| 6972455 | Flash memory structure and manufacturing method thereof A flash memory structure having high coupling ratio and the manufacturing method thereof are provided. The manufacturing method includes the following steps of method of a flash memory having high coupling ratio, including steps of providing a substrate, forming a f... | 12/06/2005 |
| 6959279 | Text-to-speech conversion system on an integrated circuit A text-to-speech conversion system that includes a first module to convert text into words, a second module to convert words into phonemes, a third module to map phonemes to sound units, and a storage unit to store speech representations for a library of sound units... | 10/25/2005 |
| 6891244 | Plug structure having low contact resistance and method of manufacturing A manufacturing method of a plug structure having low contact resistance includes the following steps. First, a silicon substrate and a BPSG layer covering thereon are provided. The silicon substrate has a dopant area. Next, the BPSG layer is etched to form a contac... | 05/10/2005 |
| 6870387 | Method and test structures for measuring interconnect coupling capacitance in an IC chip Measurement method and test structures for measuring interconnect coupling capacitance in an IC chip are provided. This method employs CBCM technique. In the first step, two test structures are used to measure a target configuration in order to obtain the total capa... | 03/22/2005 |
| 6852568 | Pin-assignment method for integrated circuit packages to increase the electro-static discharge protective capability A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-as... | 02/08/2005 |
| 6845476 | Method for testing a non-volatile memory The present invention discloses a method for testing a non-volatile memory, characterized in that the code assigned by the client is written in at least one non-volatile memory in advance, and then a particular pin of the non-volatile memory is cut, such as a write ... | 01/18/2005 |
| 6838708 | I/O cell and ESD protection circuit An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-... | 01/04/2005 |
| 6837440 | Contactless and intelligence-wise code identification chip system The present invention provides a kind of contactless and intelligence-wise code identification chip system. The contactless and intelligence-wise code identification chips have an identification code respectively. The chips can generate a random number to select one... | 01/04/2005 |
| 6831518 | Current steering circuit for amplifier The present invention provides improved techniques for controlling current flow in an amplifier circuit. Specific embodiments provide steering of analog outputs of digital to analog converters in order to drive columns of an LCD display. Embodiments can provide a fu... | 12/14/2004 |
| 6828219 | Stacked spacer structure and process A stacked spacer structure and process adapted for a stacked layer on a semiconductor substrate is described. The stacked spacer structure is formed on the sidewalls of the stacked layer which comprise a conductive layer and a cap layer thereon. A dielectric layer m... | 12/07/2004 |
| 6825100 | Method for fabricating conductive line on a wafer A method for fabricating an Al—Si—containing alloy line, which is adapted to form a conductive line on a substrate, is described. A first conductive layer, a second conductive layer and an Al—Si—containing alloy layer are sequentially formed on the substrate... | 11/30/2004 |
| 6792402 | Method and device for defining table of bit allocation in processing audio signals A method and a device for defining bit allocation table in processing audio signals are provided. The provided method and device can save storage bits and provide light quality as well. In the first step, the total number of bits for storing audio signals is determi... | 09/14/2004 |
| 6784702 | Driver circuit with dynamically adjusting output current and input current-limiting function The present invention provides a Driver circuit having dynamically adjusting output current and limiting input current function. This present invention dynamically adjusts the output current provided by the driver unit to reduce this output current in real time. A p... | 08/31/2004 |
| 6775733 | Interface for USB host controller and root hub A USB host system includes a core logic having a host controller and a first root hub coupled thereto, a second root hub external to the core logic and coupled to the first root hub via a mapping interface, and a plurality of USB ports coupled to the second root hub... | 08/10/2004 |
| 6747764 | High speed scanner A scanner has a housing, and a glass piece positioned over the housing and covering portions of the interior of the housing, with the glass piece adapted to support an image to be scanned. The scanner further includes a sensor positioned inside the housing below the... | 06/08/2004 |
| 6747491 | Spike free circuit for reducing EMI effect The present invention discloses a spike free circuit, which comprises a first flip-flop stage, a time shift means, a group of logic gates and a second flip-flop stage. The first flip-flop stage is triggered by a first edge of a clock signal. The time shift means is ... | 06/08/2004 |
| 6687830 | Energy-saving control interface and method for power-on identification An energy-saving control interface for power-on identification utilizes a first switch to start to sense and identify data. A second switch is connected to a sensing/scanning circuit for powering off the sensing/scanning circuit when a timer has reached i... | 02/03/2004 |
| 6542346 | High-voltage tolerance input buffer and ESD protection circuit A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing... | 04/01/2003 |
| 6510084 | Column decoder with increased immunity to high voltage breakdown A column decoder in an electrically-erasable, programmable read-only memory applies a bias voltage to, or floats, the gates of selected transistors during an erasure operation. This reduces the potential for gate oxide breakdown by decreasing the voltage ... | 01/21/2003 |
| 6501136 | High-speed MOSFET structure for ESD protection A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diff... | 12/31/2002 |
| 6493262 | Method for operating nonvolatile memory cells The present invention is directed at a new nonvolatile memory cell structure, and a new erase method and apparatus for operating this and other nonvolatile memory cells, with special emphasis on source-side injection flash EEPROM cells, which enhances the... | 12/10/2002 |
| 6482751 | Titanium dioxide layer serving as a mask and its removed method A titanium dioxide layer serving as a mask used in a manufacturing process of integrated circuit and its removed method are disclosed. The method includes the steps of forming a titanium dioxide layer on the integrated circuit device to serve as a mask, a... | 11/19/2002 |
| 6476451 | Buried guard rings for CMOS device A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shal... | 11/05/2002 |
| 6476449 | Silicide block for ESD protection devices A semiconductor device has a first diffusion region having a silicided portion and a non-silicided portion. The device also has a second diffusion region, and a channel region between the first and second diffusion regions. The non-silicided portion of th... | 11/05/2002 |
| 6469362 | High-gain pnp bipolar junction transistor in a CMOS device and method for forming the same An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipol... | 10/22/2002 |
| 6464562 | System and method for in-situ monitoring slurry flow rate during a chemical mechanical polishing process A system and method for in-situ monitoring slurry flow rate during a chemical mechanical polishing process is provided. The present system comprises a chemical mechanical polishing apparatus with an impact pressure measuring device. The impact pressure me... | 10/15/2002 |
| 6444401 | Fabrication of field emitting tips A method of forming a field emission device for a flat panel display includes operating a projection exposure apparatus. This comprises placing three layers of exposure sensitive material on a device in succession, with steps of exposure and removal of ma... | 09/03/2002 |
| 6437396 | Nonvolatile memory A structure and a process of a nonvolatile memory are provided. By forming a oxide/nitride/oxide (ONO) layer in a floating gate thin oxide (FLOTOX) memory, the same data can be programmed in one nonvolatile memory to guarantee the reliability but without ... | 08/20/2002 |
| 6433838 | Video signal processing method for improving the picture of dim area A method of video signal processing that reduces computational and circuit costs. The method of processing a video signal of the present invention comprises the following steps: First, receiving a video input signal including an input luminance signal and... | 08/13/2002 |
| 6414361 | Buried shallow trench isolation and method for forming the same An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench ... | 07/02/2002 |
