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| Number | Title | Issue Date |
| 8179901 | System and method for squelching a recovered clock in an ethernet network A system and method for squelching a recovered clock in an Ethernet network. In one embodiment the invention provides a method for squelching a recovered clock in an Ethernet network comprising a local node coupled to a remote node by a link, the method including re... | 05/15/2012 |
| 8009569 | System and a method for maintaining quality of service through a congested network In flow control, such as in Ethernet communication, the data is divided into queues of different priorities so that, when transmission is enabled, quality of service may be provided by first transmitting data of high priority. A networking element, such as a switch,... | 08/30/2011 |
| 7924910 | Adaptive equalization with group delay Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights t... | 04/12/2011 |
| 7839707 | Fuses for memory repair Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired... | 11/23/2010 |
| 7821290 | Differential voltage mode driver and digital impedance caliberation of same A differential voltage mode driver and digital impedance calibration of same is provided. In one embodiment, the invention relates to a method of calibrating a differential driver circuit having a plurality of parallel driver stages, the differential driver circuit ... | 10/26/2010 |
| 7817674 | Output clock adjustment for a digital I/O between physical layer device and media access controller Output clock adjustment for a digital I/O between physical layer devices and media access controller. A method is disclosed for transferring data received on the input of a physical layer device from a transmission medium to an output associated with the physical la... | 10/19/2010 |
| 7738547 | Method and apparatus for improved high-speed adaptive equalization A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred em... | 06/15/2010 |
| 7657191 | Variable bandwidth transimpedance amplifier with one-wire interface A bandwidth adjustable transimpedance amplifier. The bandwidth adjustable transimpedance amplifier includes a feedback path with a selectable resistance. The bandwidth adjustable transimpedance amplifier is preferably implemented with a photodiode in a five pin pack... | 02/02/2010 |
| 7636352 | Maintaining filtering database consistency Information is shared between switches such as bridges to facilitate efficient forwarding of data. In some embodiments consistency is maintained between information stored in filtering databases for IEEE 802.1D or 802.1Q bridges. When a switch does not have an entry... | 12/22/2009 |
| 7545817 | Data loop port acceleration circuit An apparatus associated with a device connected to a data loop processes data received from the data loop to determine whether data from the data loop is to be routed back to the data loop. The apparatus may determine how to route data based on an analysis of whethe... | 06/09/2009 |
| 7486686 | Method and apparatus for scheduling data on a medium A bandwidth guaranteeing, BW, process transmits data from a first group of queues to a medium. When none of the queues of the first group wishes to transmit data via the bandwidth guaranteeing process, a weighted fair queuing process is provided for dividing any exc... | 02/03/2009 |
| 7471751 | Power and area efficient adaptive equalization Methods, apparatuses, and systems are presented for performing channel equalization comprising receiving a signal from a channel associated with inter-symbol interference, processing the received signal to effectively apply a plurality of linearly independent impuls... | 12/30/2008 |
| 7428599 | Method for detecting link partner state during auto negotiation and switching local state to establish link Method for detecting link partner state during Auto Negotiation then switching local state to establish link. A method is disclosed for allowing a host network node to establish a compatible communication link with a link partner network node disposed on the opposit... | 09/23/2008 |
| 7406616 | Data de-skew method and system Systems and methods for deskewing parallel data lines using at least one extra channel in parallel to the parallel data lines to carry data for comparing to data on the parallel data lines. ... | 07/29/2008 |
| 7342889 | Means and a method for switching data packets or frames A switching means and method where a number of devices exchange data on a data bus. Each device has at least one data port and at least one of the devices has a plurality of data ports. The data ports may have different data rates. An arbitration takes into account ... | 03/11/2008 |
| 7331816 | High-speed data interface for connecting network devices An interface adapted for high speed data transmission between network elements that decreases signal interference and cross-talk between the wires of a cable used for connecting the network elements. Various connection schemes are used for shielded pairs of wires wi... | 02/19/2008 |
| 7305190 | Optical dispersion correction in transimpedance amplifiers A transimpedance amplifier having adjustment for optical distortion in an optical communication link. The transimpedance amplifier comprises a transimpedance stage and a post amplifier stage, which has a feedback path including an optical distortion adjustment circu... | 12/04/2007 |
| 7301997 | Method and apparatus for improved high-speed adaptive equalization A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred em... | 11/27/2007 |
| 7236084 | Crosspoint switch with switch matrix module A crosspoint switch including a switch matrix modules and programming features. A switch matrix modules include input lines tied to inputs of the switch through precompensation networks. The programming features include user initialization states and reduced and gro... | 06/26/2007 |
| 7231008 | Fast locking clock and data recovery unit A method of synchronizing a transmitter and a receiver, comprising: receiving a transmitted serial data stream. Creating an N-bit data sample from the serial data stream. Decoding the N-bit data sample by a ring decoding technique. The ring decoding technique compri... | 06/12/2007 |
| 7230923 | Time based packet scheduling and sorting system Methods and systems for controlling scheduling in a packet switching node in a network are provided which enable the scheduling of packets from different sources in an earliest deadline first order. The packets are assigned timestamp deadlines and placed in input qu... | 06/12/2007 |
| 7227878 | Differential opto-electronics transmitter A system and method for biasing the outputs of a laser modulator driver while allowing for high speed operation. A differential amplifier type modulator driver is provided which uses a reduced number of components in the high speed path. Additionally, the modulator ... | 06/05/2007 |
| 7200176 | Transformerless ethernet controller Transformerless ethernet controller. A method for isolating an ethernet controller, having a transceiver associated therewith, from a twisted wire transmission line is provided. The power supply of the transceiver is DC isolated from system power supply. The data si... | 04/03/2007 |
| 7164677 | Data switching system A data switching system comprising one or more I/O elements each comprising a plurality of first input/output ports adapted to receive and transmit data packets or cells to and from an external data network, and one or more second input/output ports adapted to recei... | 01/16/2007 |
| 7161901 | Automatic load balancing in switch fabrics A load balancing system and method for network nodes is provided. The load balancing system includes crossbar devices, queues to receive data and a load balancer. The load balancer determines the amount of data in each of the queues and sends data to specific crossb... | 01/09/2007 |
| 7158567 | Method and apparatus for improved high-speed FEC adaptive equalization A method for performing adaptive equalization is presented comprising receiving a Forward Error Correction (FEC) encoded signal from a channel, filtering the received FEC encoded signal using a filter according to at least one adjustable filter coefficient to produc... | 01/02/2007 |
| 7142596 | Integrated circuit implementation for power and area efficient adaptive equalization Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-s interference (ISI), providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a... | 11/28/2006 |
| 7132849 | Method and apparatus for configuring the operation of an integrated circuit Method and apparatus for configuring the operation of an integrated circuit. An integrated circuit with external programming capabilities is disclosed. A pin current source is provided for interfacing with at least one pin on the integrated circuit to control curren... | 11/07/2006 |
| 7123678 | RZ recovery A data and clock recovery system adapted for use with RZ data. In one embodiment a phase detector provides phase information for low to high data signal transitions only. In another embodiment a clock recovered from rising transitions is mixed with a clock recovered... | 10/17/2006 |
| 7119611 | On-chip calibrated source termination for voltage mode driver and method of calibration thereof On-chip calibrated source termination for voltage mode driver. An amplifier is disclosed having an internal amplifier with a first output and a second output, the first output interfaced to a non-inverting input through an interface. The second output is coupled to ... | 10/10/2006 |
| 7003228 | Method and apparatus for improved high-speed adaptive equalization Improved high-speed adaptive equalization is presented that may involve converting an optical signal into an electrical signal and performing equalization by (i) filtering the electrical signal with an analog filter according to at least one filter coefficient to pr... | 02/21/2006 |
| 6998292 | Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier The present invention is directed to a method and an apparatus where the standard wire bonding of TBGA's is replaced using a solid intermediate subcarrier on which the die may be flip chipped and which may then be flip chipped onto the substrate. The subcarrier has ... | 02/14/2006 |
| 6996202 | Multiple channel adaptive data recovery system A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the ... | 02/07/2006 |
| 6990162 | Scalable clock distribution for multiple CRU on the same chip A scalable clock recovery system. In one embodiment the system comprises a clock master unit, a clock distribution network, and a plurality of clock recovery units. The master clock unit generates a plurality of master clock signals, which are received by the clock ... | 01/24/2006 |
| 6948109 | Low-density parity check forward error correction A forward correction system using a linked low density parity check (LDPC) code. The linked LDPC code is formed by extending a portion of an original LDPC matrix such that the LDPC code becomes a periodic repeating code. ... | 09/20/2005 |
| 6946948 | Crosspoint switch with switch matrix module A crosspoint switch including a switch matrix modules and programming features. A switch matrix modules include input lines tied to inputs of the switch through precompensation networks. The programming features include user initialization states and reduced and gro... | 09/20/2005 |
| 6933793 | Method of overtone selection and level control in an integrated circuit CMOS negative resistance oscillator to achieve low jitter A stable high-frequency clock pulse apparatus and method including frequency source, overtone crystal unit coupled with a negative resistance oscillator, a bandpass overtone filter and a drive level control is provided. The apparatus can include a frequency multipli... | 08/23/2005 |
| 6925218 | Control techniques and devices for an optical switch array Techniques and systems for controlling an optical switch array based on local and global optical monitoring and feedback controls. Each optical switch element includes a local optical monitoring mechanism to form a local feedback control to lock the switch element a... | 08/02/2005 |
| 6904061 | Transparent transport overhead mapping A mapping operation maps identified bytes of a transport overhead of a data stream to other unused areas of the overhead. A de-mapping operation maps the bytes mapped by the mapping operation back to the locations from which the bytes were moved. A passing operation... | 06/07/2005 |
| 6873029 | Self-aligned bipolar transistor A heterojunction bipolar transistor with self-aligned features having a self-aligned dielectric sidewall spacer disposed between base contact and emitter contact, and self-aligned base mesa aligned relative to self-aligned base contact. The base contact is self-alig... | 03/29/2005 |
