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| Number | Title | Issue Date |
| 4928266 | Static ram with high speed, low power reset A static memory device is disclosed having an array of static memory cells, each memory cell having first and second cross-coupled inverters. All of the memory cells have distinct power voltage connections to the first and second inverters of each memory ... | 05/22/1990 |
| 4843264 | Dynamic sense amplifier for CMOS static RAM A sense amplifier for use in a CMOS static random access memory. The core of the sense amplifier comprises seven transistors: two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from th... | 06/27/1989 |
| 4719602 | Memory with improved column access A semiconductor memory device having an improved system for randomly accessing a preselected set of memory locations. The invention includes a set of "secondary sense amplifiers" which act as a high speed buffer between the memory's normal sense amplifier... | 01/12/1988 |
| 4679171 | MOS/CMOS memory cell A memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal... | 07/07/1987 |
| 4675848 | Dynamic RAM memory There is provided an improved MOS dynamic random access memory (DRAM) device having an array of dynamic RAM cells accessed by word and bit lines. Each memory cell comprises a single field-effect transistor coupled by its source to the gate of an MOS stora... | 06/23/1987 |
| 4667311 | Dynamic ram with reduced substrate noise and equal access and cycle time There is described a CMOS random access memory having memory access circuitry which substantially eliminates substrate noise caused by capacitive coupling of the bit lines to the substrate, and which allows the memory to have equal length access and cycle... | 05/19/1987 |
