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"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 8149334 | PIP processing apparatus and method thereof A PIP (Picture In Picture) processing apparatus processes a main image and a secondary image and includes a scaling circuit, a memory circuit, a first selecting circuit and a processing circuit. The scaling circuit scales down the secondary image to output a scaled-... | 04/03/2012 |
| 8146108 | Driver assisted asynchronous command processing A method for assisting multi-threaded command execution by a driver in a multi-core computer system, is disclosed. The method includes distinguishing asynchronous commands from synchronous commands, buffering the asynchronous commands in a buffer, processing the syn... | 03/27/2012 |
| 8146061 | Systems and methods for graphics hardware design debugging and verification Disclosed are systems and methods for debugging and analyzing graphics hardware designs. Hardware designs are represented by a software model implemented in a programming language. Graphics operations can be executed in the software model as well as in reference sof... | 03/27/2012 |
| 8144149 | System and method for dynamically load balancing multiple shader stages in a shared pool of processing units The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a ... | 03/27/2012 |
| 8134898 | Method and device for protecting a PLL in reading signals on a defect disc A device for protecting a PLL in reading signals on a defect disc from disturbance and instability is provided. The device includes a defect detection unit, a logic combination unit and a PLL. The defect detection unit receives a plurality of defect detection signal... | 03/13/2012 |
| 8121001 | Method and device for protecting a servo in reading signals on a defect disc A device for protecting a servo in reading signals on a defect disc from disturbance and instability is provided. The device includes a defect detection unit and a logic combination unit. The defect detection unit receives a plurality of defect detection signals to ... | 02/21/2012 |
| 8107761 | Method for determining boundary strength A method for determining the boundary strengths of edges in a block-based digitally encoded image is disclosed. The method includes setting the boundary strength of two adjacent blocks in an Inter macroblock to a first strength value if any one of the two adjacent b... | 01/31/2012 |
| 8098974 | Method and system of format converting and recording for optical storage media A format converting and recording method and system for optical storage media including the steps of converting several first optical storage medium information files into the second optical storage medium through generating corresponding navigation tables which gat... | 01/17/2012 |
| 8098264 | Method and apparatus for rendering computer graphics primitive The present invention is directed to a method for rendering a computer graphics primitive intersected with one or more user-defined clipping planes. The method includes receiving a primitive, a clipping plane and a default scissor window; determining a second scisso... | 01/17/2012 |
| 8085274 | Video data compression Systems and methods for compressing data within a block of data for storage in memory and for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be stored more efficiently and transmitted in few... | 12/27/2011 |
| 8085062 | Configurable bus termination for multi-core/multi-package processor configurations A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termi... | 12/27/2011 |
| 8082426 | Support of a plurality of graphic processing units Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data related to a status of at least one context and a context switch configura... | 12/20/2011 |
| 8080978 | Battery charging system and method Methods, devices, and systems for charging a battery in a mobile device are provided. For example, in one embodiment, among others, a battery charging system includes a monitoring circuit configured to monitor a battery and generate a sense current. The battery char... | 12/20/2011 |
| 8079027 | Programming language translation systems and methods Included are embodiments of a description language program stored in a computing device for updating a first version of a computer program. In at least one embodiment, the first version of the computer program is written in a universal format and the program include... | 12/13/2011 |
| 8068120 | Guard band clipping systems and methods The present disclosure provides embodiments of guard band clipping systems and methods. One guard band clipping system embodiment, among others, includes a vertex processor configured to convert transformed vertex data to integer screen space data and pass the trans... | 11/29/2011 |
| 8064524 | De-interlacing method and apparatus using remote interpolation The present invention is directed to de-interlacing method and apparatus using remote interpolation. An up window and a down window are firstly determined. The closest pair of pixels of the up window and the down window along a direction of 90°, −45°, and 45° i... | 11/22/2011 |
| 8028107 | Apparatus and method for serial to parallel in an I/O circuit A serial to parallel I/O circuit apparatus includes M sequential logic circuits and each of them includes a first D-type flip-flop for receiving one bit of input data, and the output of each the first D-type flip-flop connects to the input of a first D-type flip-flo... | 09/27/2011 |
| 8024394 | Dual mode floating point multiply accumulate unit Included are embodiments of a Multiply-Accumulate Unit to process multiple format floating point operands. For short format operands, embodiments of the Multiply Accumulate Unit are configured to process data with twice the throughput as long and mixed format data. ... | 09/20/2011 |
| 8022909 | System, method, and apparatus for generating grayscales in an LCD panel Discussed herein is a circuit for generating grayscales in a display. The circuit generally comprises grayscale values, one of which is a present grayscale value. Also included is at least one grayscale pattern, comprising at least one pattern bit and corresponding ... | 09/20/2011 |
| 8019906 | Dual mode displayport (DP) and high definition multimedia interface (HDMI) transmitter configured to transmit video and/or audio signals in DP or HDMI according to mode signal A system and method for dual mode DP and HDMI transmission are provided. Briefly described, one embodiment of a dual mode DP and HDMI transmitter, among others, can be implemented as follows. The dual mode DP and HDMI transmitter comprises a driver circuit controlle... | 09/13/2011 |
| 8018698 | I/O circuit with ESD protecting function For ensuring the complete turn-off state of an ESD protecting device and preventing leakage current from a chip, an alternative conducting path is formed in the chip for bypassing an external current. The chip further includes an internal circuit and a conducting ci... | 09/13/2011 |
| 8014440 | Frequency adjusting method of a CDR circuit and apparatus thereof A frequency adjusting method of a CDR circuit and apparatus thereof are provided. The adjusting method is applied to a receiver apparatus connected to an outer apparatus. The outer apparatus, after actuated, sends out an outer data signal to the receiver apparatus a... | 09/06/2011 |
| 8005318 | Weight-adjusted module and method A weight-adjusted method applied in adjusting a weighting coefficient in an image scaling process. First, an absolute difference is obtained by taking an absolute value of a difference between a first pixel value and a second pixel value of an image. Next, the absol... | 08/23/2011 |
| 8004533 | Graphics input command stream scheduling method and apparatus A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second com... | 08/23/2011 |
| 8004531 | Multiple graphics processor systems and methods Multiple graphics processor system and method embodiments are disclosed. One system embodiment, among others, comprises a multiple graphics processor system, comprising a first graphics processing unit having first status information and a second graphics processing... | 08/23/2011 |
| 7999819 | Systems and methods for managing texture descriptors in a shared texture engine Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corr... | 08/16/2011 |
| 7991990 | Memory access system and memory access method thereof A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memor... | 08/02/2011 |
| 7987408 | Data buffering method In a data processing and buffering method, at least one read cycles are asserted to obtain at least one data, respectively, wherein each of the data includes at least one sub data and each data is specified with an address pointer and an enable bit array. When a cer... | 07/26/2011 |
| 7986036 | Power/ground network of integrated circuits and arrangement thereof An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The h... | 07/26/2011 |
| 7975132 | Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and d... | 07/05/2011 |
| 7965296 | Systems and methods for storing texture map data Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at... | 06/21/2011 |
| 7958383 | Computer system with adjustable data transmission rate A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data tr... | 06/07/2011 |
| 7949509 | Method and tool for generating simulation case for IC device For generating a simulation case to verify an operation of an IC device, a database including a plurality of device description files, a plurality of pattern files and a plurality of command files is established. Files stored in the database and corresponding to an ... | 05/24/2011 |
| 7948497 | Chipset and related method of processing graphic signals A chipset is electrically connected with an external graphic module, which generates a first graphic signal and outputs it to the chipset. The chipset includes an internal graphic module and a control module. The internal graphic module generates a second graphic si... | 05/24/2011 |
| 7940087 | Clockless return to state domino logic gate A clockless return to state domino logic gate is disclosed responsive to multiple return to state input nodes. A domino circuit has a preset state in which it presets a preset node to a second state. The domino circuit switches to a latch state and switches an outpu... | 05/10/2011 |
| 7937561 | Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstructio... | 05/03/2011 |
| 7930671 | Test method for unit re-modification The present invention described a test method for unit re-modification, in which there is a test end and a host end. The method generated a sample pattern at a test end, generates a control pattern and modifies a re-modification unit. Otherwise, an experimental patt... | 04/19/2011 |
| 7929983 | Method and apparatus for neighbor cell synchronization The present invention is directed to a neighbor cell synchronization method for a mobile communication unit. The method includes selecting a neighbor cell according to a scheduling mechanism; determining a synchronization window according to a communicating mode of ... | 04/19/2011 |
| 7929389 | Optimum power calibration method and optical disk drive An optimum power calibration method is provided and is implemented for writing a rewritable optical storage medium including a power calibration area. The method includes the steps of determining whether the power calibration area is recorded with data, erasing the ... | 04/19/2011 |
| 7925891 | Apparatus and method for employing cryptographic functions to generate a message digest The present invention provides an apparatus and method for performing cryptographic operations on a plurality of message blocks within a processor to generate a message digest. In one embodiment, the apparatus has an x86-compatible microprocessor that includes trans... | 04/12/2011 |
