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| Number | Title | Issue Date |
| 8149901 | Channel switching circuit An active routing circuit. In representative embodiments, the active routing circuit includes a channel switch which includes a transceiver and a switch. The transceiver has first data line, second data line, drive/receive control line, and receiver select control l... | 04/03/2012 |
| 8131531 | System and method for simulating a semiconductor wafer prober and a class memory test handler A method runs a simulation. The method comprises receiving a selection of a device. The device is one of a prober used in wafer testing and a handler used in package testing. The method comprises receiving at least one parameter for a set of parameters for the simul... | 03/06/2012 |
| 8127186 | Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the l... | 02/28/2012 |
| 8068537 | Communication circuit for a bi-directional data transmission A communication circuit for providing a bi-directional data transmission over a signal line, thereby receiving a first digital data stream and transmitting a corresponding first signal into a near end of a signal line to a remote device, the remote device being conn... | 11/29/2011 |
| 8060851 | Method for operating a secure semiconductor IP server to support failure analysis A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically th... | 11/15/2011 |
| 8010933 | Source synchronous timing extraction, cyclization and sampling A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the ... | 08/30/2011 |
| 8010856 | Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The... | 08/30/2011 |
| 8008933 | System and method for baseband calibration A system includes at least one of a first generator, at least two of a second generator, and a load board. The at least one of a first generator one of receives and transmits analog signals. The at least two of a second generator one of receives and transmits digita... | 08/30/2011 |
| 8006149 | System and method for device performance characterization in physical and logical domains with AC SCAN testing A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The me... | 08/23/2011 |
| 8005633 | Excitation signal generator for improved accuracy of model-based testing An excitation signal generator (“ESG”) is described. The ESG generates an minimized excitation signal for use in a test system to generate a functional model of a device under test (“DUT”) where extreme values of the minimized excitation signal are increased... | 08/23/2011 |
| 7952373 | Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits o... | 05/31/2011 |
| 7934710 | Clamp and method for operating same In an embodiment, there is disclosed a clamp having a frame and a latch member mounted within the housing so that the latch member is translatable along a displacement axis and rotatable about the displacement axis. A cam follower mounted to the frame engages a chan... | 05/03/2011 |
| 7930603 | Feature-oriented test program development and execution A resource constraint management unit for a target test system is described. The resource constraint management unit has an interface adapted for receiving, together with a test program, feature specifications for at least one test of the test program, said feature ... | 04/19/2011 |
| 7928755 | Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function... | 04/19/2011 |
| 7924043 | Method and product for testing a device under test In a method of testing a device under test (DUT) using a test device adapted to provide a connection to a central controller, a test procedure activation signal is supplied from the central controller to the test device. A test procedure for testing the DUT is perfo... | 04/12/2011 |
| 7921381 | Method and apparatus for displaying test data In one embodiment, a plurality of test data entries are successively displayed via a graphical user interface (GUI), with each of the test data entries including at least a test result identifier and a corresponding test result. For at least one of the test data ent... | 04/05/2011 |
| 7893695 | Apparatus, method, and computer program for obtaining a time-domain-reflection response-information An apparatus for obtaining a time-domain-reflection response-information has a signal driver adapted to apply two pulses of different pulse lengths to a TDR port in order to excite a first TDR response signal corresponding to a first pulse and a second TDR response ... | 02/22/2011 |
| 7847716 | Asynchronous sigma-delta digital-analog converter An asynchronous sigma delta digital to analog converter for converting a digital input signal into an analog output signal, the digital to analog converter having an asynchronous sigma delta modulator having a low pass filter and a comparator and being supplied with... | 12/07/2010 |
| 7865788 | Dynamic mask memory for serial scan testing A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs. | 01/04/2011 |
| 7859277 | Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array Apparatus is for processing signals between a tester and devices under test. In one embodiment, the apparatus includes at least one multichip module. Each multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester ... | 12/28/2010 |
| 7853846 | Locating hold time violations in scan chains by generating patterns on ATE A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a... | 12/14/2010 |
| 7853828 | Graphically extensible, hardware independent method to inspect and modify state of test equipment A hardware independent and graphically extensible tester state browsing technique for observing and modifying operating state of test equipment includes accessing a descriptor file describing an architecture of the test equipment, invoking a set of plugins associate... | 12/14/2010 |
| 7827452 | Error catch RAM support using fan-out/fan-in matrix In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for inpu... | 11/02/2010 |
| 7823128 | Apparatus, system and/or method for combining multiple tests to a single test in a multiple independent port test environment Test development tools, systems and/or methods which include accessing first and second pre-established test programs, each of said first and second pre-established test programs having been previously established for respective first and second pre-existing integra... | 10/26/2010 |
| 7821254 | Method and apparatus for improving load time for automated test equipment An SOC tester having test cards with memory cards is presented. The SOC tester may be running a test on a device under test using test programs stored on one set of memory cards. Test programs may be down loaded to a second set of memory cards during testing using t... | 10/26/2010 |
| 7812626 | High density interconnect system for IC packages and interconnect assemblies An improved interconnection system is described, such as for electrical contactors and connectors, electronic device or module package assemblies, socket assemblies, and/or probe card assembly systems. An exemplary connector comprises a first connector structure com... | 10/12/2010 |
| 7797599 | Diagnostic information capture from logic devices with built-in self test From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to t... | 09/14/2010 |
| 7791525 | Time-to-digital conversion with calibration pulse injection A time-to-digital converter having at least one chain of delay elements, wherein a status of the chain of delay elements represents a digital signal relating to a time interval to be converted, wherein the time-to-digital converter having an injector for injecting a... | 09/07/2010 |
| 7782242 | Time-to-digital conversion with delay contribution determination of delay elements A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distrib... | 08/24/2010 |
| 7768278 | High impedance, high parallelism, high temperature memory test system architecture An electronic device for use with a probe head in automated test equipment. The device includes a plurality of semiconductor devices arranged to provide at least one driver/receiver pair where the driver portion of the driver/receiver pair is configured to transmit ... | 08/03/2010 |
| 7750650 | Solid high aspect ratio via hole used for burn-in boards, wafer sort probe cards, and package test load boards with electronic circuitry A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one s... | 07/06/2010 |
| 7743304 | Test system and method for testing electronic devices using a pipelined testing architecture A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test contr... | 06/22/2010 |
| 7734848 | System and method for frequency offset testing Described is a system and method for frequency offset testing. The system comprises an electronic device, a first testing device providing a reference clock signal at a first frequency to the electronic device, and a second testing device receiving data from the ele... | 06/08/2010 |
| 7720793 | Method and system for selectively processing test data using subscriptions in a multi-formatter architecture In an embodiment, there is disclosed a system for selectively processing test data using subscriptions in a multi-formatter architecture. The system includes a set of designators specifying types of data; a set of formatters for writing data to files; and a monitor ... | 05/18/2010 |
| 7717715 | System, method and apparatus using at least one flex circuit to connect a printed circuit board and a socket card assembly that are oriented at a right angle to one another There is disclosed apparatus for routing signals between at least one PCB within a test head and a socket card assembly. In an embodiment, the apparatus may include at least one flexible circuit electrically connecting first and second sides of the PCB and the socke... | 05/18/2010 |
| 7712000 | ATE architecture and method for DFT oriented testing An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK ... | 05/04/2010 |
| 7711524 | Estimating boundaries of Schmoo plots A method and system generate a boundary of a Schmoo plot. In accord with the method, a plurality of seed points having a resolution that is less than or equal to ½ the acquisition resolution indicated by a smoothness of a representative Schmoo boundary are selected... | 05/04/2010 |
| 7676347 | Systems and methods for accumulation of summaries of test data In one embodiment, there is disclosed a system for accumulation of summaries of test data. The system includes a data populator having code to: (1) generate data objects from the test data and store the data objects in a data model, (2) arrange the data objects in a... | 03/09/2010 |
| 7650547 | Apparatus for locating a defect in a scan chain while testing digital logic An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns. ... | 01/19/2010 |
| 7644213 | Resource access manager for controlling access to a limited-access resource Methods and devices utilizing operating system semaphores are described for managing access to limited-access resources by clients. ... | 01/05/2010 |
