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| Number | Title | Issue Date |
| 7574468 | Digital signal processor having inverse discrete cosine transform engine for video decoding and partitioned distributed arithmetic multiply/accumulate unit therefor A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations (IDCTs). In one embodiment, the distributed arithmetic MAC unit includes: (1) a first pipeline stage configured to perform dot products on received sequenti... | 08/11/2009 |
| 7418578 | Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a co... | 08/26/2008 |
| 7360117 | In-circuit emulation debugger and method of operation thereof An in-circuit emulation debugger and method of operating an in-circuit emulation debugger to test a digital signal processor (DSP). In one embodiment, the in-circuit emulation debugger includes: (1) a device emulation unit, coupled to a collocated DSP core, for emul... | 04/15/2008 |
| 7299343 | System and method for cooperative execution of multiple branching instructions in a processor A system for conditionally executing an instruction depending on a previously existing condition. The system disclosed is configured to handle conditional execution instructions typically specifying at least one target instruction, a processor register, and a condit... | 11/20/2007 |
| 7275149 | System and method for evaluating and efficiently executing conditional instructions A system, circuit, and method are presented for evaluating conditional execution instructions. The system, circuit, and method are adapted to receive an identification instruction comprising the size and the condition of execution of a block of conditional execution... | 09/25/2007 |
| 7272704 | Hardware looping mechanism and method for efficient execution of discontinuity instructions A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or superscalar processor. For example, the hardware looping mechanism may ... | 09/18/2007 |
| 7251721 | Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers through each corresponding register of said register sets as instructions move through the pipeline For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state... | 07/31/2007 |
| 7231510 | Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue architecture, and a digital signal processor (DSP) incorporating the mechani... | 06/12/2007 |
