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| Number | Title | Issue Date |
| 6549563 | Methods and apparatus for use in generating spreading sequences for multiple modes of communication In one example described, a data sequence generator for use in spread spectrum communications includes one or more read-only memories (ROMs) which have first and second spreading sequences stored therein. The first spreading sequence is associated with a ... | 04/15/2003 |
| 6539049 | Device and method for maintaining time synchronous with a network master time An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital tr... | 03/25/2003 |
| 6487242 | Method and apparatus for VCO modulation in a communication system A VCO modulator controller including a ROM memory storing a number of waveform maps, a counter coupled to the ROM memory and capable of developing a sequence of ROM addresses, a temporal bit generator responsive to a data stream to develop a next bit Nb, ... | 11/26/2002 |
| 6472253 | Programmable semiconductor device structures and methods for making the same A programmable device and methods for making the programmable device are provided. The programmable device includes a link metallization line with an oxide layer defined above the link metallization line. A via hole is patterned in the oxide layer which d... | 10/29/2002 |
| 6452959 | Method of and apparatus for generating data sequences for use in communications A method of generating one or more pseudorandom noise (PN) sequences for use in spread spectrum communications includes the steps of providing data at an input of memory which stores bits associated with a pseudorandom noise (PN) sequence: changing the da... | 09/17/2002 |
| 6424180 | Digital phase shift amplification and detection system and method A digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is f... | 07/23/2002 |
| 6411367 | Modified optics for imaging of lens limited subresolution features A system and method is disclosed for enhancing an optical lithography process by capturing light diffracted from a mask having features to be exposed onto a wafer. In one embodiment, a system of the present invention has in place a mask, a wafer and a red... | 06/25/2002 |
| 6410440 | Method and apparatus for a gaseous environment providing improved control of CMP process A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a ... | 06/25/2002 |
| 6400728 | Method and system for detecting user data types in digital communications channels and optimizing encoding-error correction in response thereto A dynamic error correction system for a digital data transmission system. A transmitter adapted to encode user data into a signal is included within the system. A receiver receives the signal and decodes the user data encoded thereon. The signal is transm... | 06/04/2002 |
| 6397279 | Smart retry system that reduces wasted bus transactions associated with master retries The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus.... | 05/28/2002 |
| 6380001 | Flexible pin count package for semiconductor device A package for a semiconductor device and a method for packaging a semiconductor device are disclosed. The semiconductor package uses a tape which allows for the production of packaged semiconductor devices having different contact patterns. The contact pa... | 04/30/2002 |
| 6380092 | Gas phase planarization process for semiconductor wafers A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a p... | 04/30/2002 |
| 6378044 | Method and system for cache replacement among configurable cache sets A method and system for cache replacement among configurable cache sets. In one embodiment, the present invention identifies a cache location corresponding to uncached data received from main memory and determines a data type for the uncached data. The pr... | 04/23/2002 |
| 6377581 | Optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks An optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks. A system in accordance with the present invention communicatively couples the internal components (e.g., CPU, memory, etc.) and peripheral devices ... | 04/23/2002 |
| 6374398 | Efficient database for die-per-wafer computations A method and system thereof for efficiently computing the number of dies per wafer and the corresponding number of stepper shot counts. Dimensions for a die and the size of the wafer are received. The dimensions comprise a die element size that is a funct... | 04/16/2002 |
| 6372522 | Use of optimized film stacks for increasing absorption for laser repair of fuse links A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included... | 04/16/2002 |
| 6363466 | Interface and process for handling out-of-order data transactions and synchronizing events in a split-bus system An interface and process for re-ordering data transactions between a master device and a target device. The present invention applies to target devices that interface to master devices such that both masters and slaves are capable of handling the re-order... | 03/26/2002 |
| 6360754 | Method of protecting quartz hardware from etching during plasma-enhanced cleaning of a semiconductor processing chamber The present invention is a method of suppressing etchrate of quartz hardware in semiconductor processing chamber during plasma-enhanced cleaning. In one embodiment, the method of the present invention includes the steps of: (a) introducing a mixture of fl... | 03/26/2002 |
| 6356610 | System to avoid unstable data transfer between digital systems A system to avoid unstable data transfer between digital systems. The present invention includes a system that enables digital systems to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. For insta... | 03/12/2002 |
| 6353904 | Method of automatically generating new test programs for mixed-signal integrated circuit based on reusable test-block templates according to user-provided driver file A method of automatically generating a mixed-signal test program. The method according to one embodiment of the present invention is implemented in software in the form of two software processes. The first software process of the present embodiment includ... | 03/05/2002 |
| 6353261 | Method and apparatus for reducing interconnect resistance using an interconnect well An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit... | 03/05/2002 |
| 6353368 | VCO circuit using negative feedback to reduce phase noise A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage convert... | 03/05/2002 |
| 6346032 | Fluid dispensing fixed abrasive polishing pad The present invention is a fluid dispensing fixed abrasive polishing pad CMP system and method that utilizes fixed abrasive components to remove a portion or entire layer of a wafer while dispensing a fluid without suspended abrasive particles onto the wa... | 02/12/2002 |
| 6341998 | Integrated circuit (IC) plating deposition system and method The present invention system and method facilitates efficient material deposition and wafer planarization during IC wafer fabrication. The present invention is particularly useful in facilitating efficient copper deposition and manufacturing of interconne... | 01/29/2002 |
| 6338158 | Custom IC hardware modeling using standard ICs for use in IC design validation Testing and validation of custom IC designs is performed using standard ICs. Highly complex integrated circuits, instead of being designed at the gates and flops level, are typically designed using standardized cell libraries that allow for widespread, sy... | 01/08/2002 |
| 6330623 | System and method for maximizing DMA transfers of arbitrarily aligned data A direct memory access engine (DMA) system and method for maximizing DMA transfers of arbitrarily aligned data. The present invention utilizes physical region descriptors (PRD) stored in memory to track locations and descriptions of scattered data in a ma... | 12/11/2001 |
| 6326283 | Trench-diffusion corner rounding in a shallow-trench (STI) process An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer o... | 12/04/2001 |
| 6324663 | System and method to test internal PCI agents The present invention is an on board internal peripheral component interconnect (PCI) bus tester for testing internal components of a microelectronic chip. The present invention includes internal PCI testing agents that facilitate the application of test ... | 11/27/2001 |
| 6323520 | Method for forming channel-region doping profile for semiconductor device A method for forming a semiconductor device with a doped channel-region, and the device formed therefrom. In one embodiment, the method invention is comprised of two principal steps. The first step is to provide a semiconductor substrate to which the foll... | 11/27/2001 |
| 6321321 | Set-associative cache-management method with parallel and single-set sequential reads A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is use... | 11/20/2001 |
| 6319796 | Manufacture of an integrated circuit isolation structure Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate ... | 11/20/2001 |
| 6315645 | Patterned polishing pad for use in chemical mechanical polishing of semiconductor wafers A patterned polishing pad adapted for use in a wafer polishing machine. The patterned polishing pad has a polishing surface adapted to contact frictionally a semiconductor wafer being polished in a chemical mechanical polishing machine. The polishing surf... | 11/13/2001 |
| 6316834 | Tungsten plugs for integrated circuits and method for making same A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) spu... | 11/13/2001 |
| 6314154 | Non-power-of-two Gray-code counter and binary incrementer therefor Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code... | 11/06/2001 |
| 6309937 | Method of making shallow junction semiconductor devices Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and ... | 10/30/2001 |
| 6311318 | Design for test area optimization algorithm A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an in... | 10/30/2001 |
| 6311248 | Method and system for optimized data transfers in a mixed 64-bit/32-bit PCI environment A method for optimizing the performance of a 64-bit PCI initiator when transferring a 64-bit data via a 64-bit PCI bus. The 64-bit PCI initiator receives a single 64-bit data for transfer via the 64-bit PCI bus. The 64-bit PCI initiator breaks the 64-bit ... | 10/30/2001 |
| 6309948 | Method for fabrication of a semiconductor device A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resist... | 10/30/2001 |
| 6303504 | Method of improving process robustness of nickel salicide in semiconductors After a metal deposition preclean, a very thin titanium layer is deposited followed by a thick nickel layer on a semiconductor silicon substrate. The titanium and nickel are deposited sequentially in a vacuum cluster tool to prevent oxidation of titanium ... | 10/16/2001 |
| 6301632 | Direct memory access system and method to bridge PCI bus protocols and hitachi SH4 protocols The present invention is a direct access bridge for translating messages between a first protocol and a second protocol via a first component interface and a second component interface. The first and second component interfaces are adapted to respectively... | 10/09/2001 |
