Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 8166226 | Apparatus and related method for maintaining read caching data of south bridge with north bridge A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically ... | 04/24/2012 |
| 8051350 | Serial interface device built-in self test A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer.... | 11/01/2011 |
| 8010775 | Method and related apparatus for reducing CHIPSET power consumption A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required... | 08/30/2011 |
| 7949695 | Two's complement circuit A operator is located between two converters that convert data between floating-point format and a predetermined format. The operator operates on predetermined format data, which consists of the same sign bit, the same exponent, and the two's complement of the manti... | 05/24/2011 |
| 7853843 | Method and system for testing chips Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control sig... | 12/14/2010 |
| 7825691 | Transmission circuit and related method A transmission circuit and related method are disclosed. A transmitter in the transmission circuit has CMOS transistors as driving units for responding an input signal to drive an output signal at an output node, and each driving unit has a corresponding charge unit... | 11/02/2010 |
| 7822040 | Method for increasing network transmission efficiency by increasing a data updating rate of a memory A network interface circuit or card has a memory and a medium control module for transmitting data stored in the memory to a network. The method includes: when a packet data is transmitted (such as completely transmitted) from the memory to the medium control module... | 10/26/2010 |
| 7804671 | Electrostatic discharge protection circuit An electrostatic discharge protection circuit has a substrate; a first P-well installed on the substrate and having a first P+-doped region and a first N+-doped region, both of which are connected to ground; a second P-well installed on the substrate and having a se... | 09/28/2010 |
| 7779400 | System and method for modifying firmware of an optical storage medium device without requiring a compiling process Firmware of an optical storage medium device includes an executable program code and at least one reference data set. A method for modifying the firmware without requiring a compiling process includes inputting an attribute data set for setting a user interface; mod... | 08/17/2010 |
| 7779314 | System and related method for chip I/O test System and related method for testing a chip with a high-speed bus interface in a low speed testing environment is provided. The testing method for testing input/output functions of a chip includes: establishing an inner loop path between a transmission mechanism an... | 08/17/2010 |
| 7779215 | Method and related apparatus for accessing memory A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arra... | 08/17/2010 |
| 7742061 | Method and related apparatus for image processing Method and related apparatus for image processing. When projecting a polygonal object in three-dimensional space onto a two-dimensional screen according to a viewing range, faces of the object which intersect boundaries of the viewing range are clipped to form clipp... | 06/22/2010 |
| 7710207 | Voltage controlled oscillator with improved voltage oscillation frequency characteristic A voltage controlled oscillator (VCO) with improved frequency characteristics is provided. The VCO includes a converting circuit supplied between a bias voltage and a ground voltage for converting the control voltage into a control current, a replica bias circuit co... | 05/04/2010 |
| 7681174 | Computer system and related method for generating program codes describing relationships of numerous function names and numerous control codes of a device A method for generating program code used to describe relationships between a plurality of function names and a plurality of control codes of a device. The method comprises receiving the relationships between the plurality of function names and the plurality of cont... | 03/16/2010 |
| 7676821 | Method and related system for detecting advertising sections of video signal by integrating results based on different detecting rules Method and related system for detecting advertising sections of video signal. The invention is capable of integrating detecting results based on different detecting rules, which includes detecting discontinuity of frame images in the video signals, detecting occurre... | 03/09/2010 |
| 7657704 | Method and related apparatus for verifying array of disks When receiving a verification command for verifying a part of the disk array, each of the disks of the disk array are simultaneously verified such that a part of the disk array practically verified is larger than the part assigned to be verified in the verification ... | 02/02/2010 |
| 7646818 | Method and related system for high efficiency advertising detection In the video signals provided by broadcasting media, advertising sections are inserted between normal programs, thus causing interruption. An end portion of the normal program will be repeated before an advertising section ends. The invention determines the continui... | 01/12/2010 |
| 7640383 | Method and related apparatus for configuring lanes to access ports A method and related apparatus for different lane and access port configurations of a bus. Such different configurations can apply to different applications requirements. In a preferred embodiment of the invention, a chipset can configure 18 lanes t... | 12/29/2009 |
| 7610465 | Method and related apparatus for data migration utilizing disk arrays Method and related apparatus for data migration of a disk array. While striping and migrating data of a source disk of the disk array, data stripes are grouped into different zones; after completely writing data stripes of a given zone to disks of the disk array, da... | 10/27/2009 |
| 7610454 | Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system.... | 10/27/2009 |
| 7587651 | Method and related apparatus for calibrating signal driving parameters between chips A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test ... | 09/08/2009 |
| 7567468 | Selective discharging memory circuit with reduced power consumption In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory... | 07/28/2009 |
| 7539984 | Method and apparatus for simulating a video disc player A method for simulating video disc players includes loading firmware into memory for controlling a video disc player with an operating system. The method also includes and performing the following steps with the firmware: playing the video disc, loading a set of com... | 05/26/2009 |
| 7532560 | Signal processing circuit for optical disc drivers and the related method A signal processing circuit for adjusting an input signal and generating a corresponding digital output signal in an optical disk driver is provided. The signal processing circuit includes an attenuator for receiving and attenuating the input signal and then generat... | 05/12/2009 |
| 7516374 | Testing circuit and related method of injecting a time jitter A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined mea... | 04/07/2009 |
| 7490278 | PCI express physical layer built-in self test architecture A built-in self test circuit includes a first pattern generator, an elastic buffer receiver, a command symbol detector, a second pattern generator, and a logic unit. The architecture is capable of compensating loopback latency automatically without having to utilize... | 02/10/2009 |
| 7472232 | Method and related apparatus for internal data accessing of computer system Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single vi... | 12/30/2008 |
| 7469352 | Method and related apparatus for reducing chipset power consumption A chipset has a plurality of driving units, each unit connecting to an address pin of a memory module for driving a one-bit address signal while accessing the memory module. The method detects configurations of memory modules, and determines which address pins are u... | 12/23/2008 |
| 7457972 | South and north bridge and related computer system for supporting CPU A circuit, designed for supporting a computer system having a CPU, a monitor, and a system memory electrically connected to the CPU, includes a south bridge, and a north bridge electrically connected to the south bridge, the CPU, and the monitor. The north bridge in... | 11/25/2008 |
| 7451240 | Method and related circuit for increasing network transmission efficiency by increasing a data updating rate of a memory A network interface circuit or card has a memory and a medium control module for transmitting data stored in the memory to a network. The method includes: when a packet data is transmitted (such as completely transmitted) from the memory to the medium control module... | 11/11/2008 |
| 7447827 | Multi-port bridge device A bridge device electrically connected to a first AGP bus, a second AGP bus, and a PCI bus is provided. The bridge device has a first bridge, a second bridge, and a controller. The first bridge is electrically connected between the first AGP bus and the second AGP b... | 11/04/2008 |
| 7446991 | ESD protection circuits and related techniques An electro-static discharge, ESD, protection circuit is disclosed. While protecting an ESD event between a given pad and a ground pad, the ESD protection circuit triggers a clamp for ESD protection according to a voltage difference between the given pad and a power ... | 11/04/2008 |
| 7444535 | Method and related apparatus for adjusting timing of memory signals A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger... | 10/28/2008 |
| 7444122 | Communications system with variable load and related method A mobile system has a frequency synthesizer and an amplifier module coupled to the frequency synthesizer. The frequency synthesizer is controlled by frequency division data to generate a tuning signal with a frequency corresponding to a reference signal and the freq... | 10/28/2008 |
| 7443706 | High-performance memory and related method In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory... | 10/28/2008 |
| 7443211 | Transmitter and transmission circuit Transmitter and transmission circuit. For realizing a differential transmitter, a switch circuit is connected between two load transistors of two complementary MOS pairs. The switch circuit can have two inductors. When the two complementary MOS pairs are conducting ... | 10/28/2008 |
| 7429893 | Variable-gain amplifier and related method A variable gain amplifier, VGA, and related method are provided. A reference current variably controlled by a control signal is provided, then the reference current is divided to a load current and an input-control current according to differential driving between a... | 09/30/2008 |
| 7428276 | Method and apparatus for channel impulse response estimation in GSM systems A method for estimating channel impulse response (CIR) in a communication system includes converting RF analog signals to obtain baseband digitized signals, sampling the baseband digitized signals according to the symbol period or bit period, cross-correlating at le... | 09/23/2008 |
| 7424271 | Multi-mode and multi-band RF transceiver and related communications method A multimode communications system includes a first communications module, a transmission module, a switch and a second communications module. The first communication module has a frequency modulator for modulating a dividing ratio to adjust an oscillating signal and... | 09/09/2008 |
| 7418617 | Apparatus for adjusting timing of memory signals An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit c... | 08/26/2008 |
