Assignee: United Microelectronics Corp.

Location: Hsinchu, TW
No. of patents: 202

Number	Title	Issue Date
8183103	Integrated circuit structure including schottky diode and method for manufacturing the same A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of t...	05/22/2012
8151221	Method to compensate optical proximity correction A method to compensate optical proximity correction adapted for a photolithography process is provided. An integrated circuit (IC) layout firstly is provided. The IC layout includes active regions and a shallow trench isolation (STI) region. The STI region is a regi...	04/03/2012
8139907	Optoelectronic device and method of forming the same An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the fi...	03/20/2012
8139697	Sampling method and data recovery circuit using the same A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first...	03/20/2012
8137472	Semiconductor process A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a ...	03/20/2012
8134215	MEMS diaphragm A microelectromechanical system (MEMS) diaphragm is provided. The MEMS diaphragm includes a first conductive layer, a second conductive layer and a dielectric layer. The first conductive layer is disposed on a substrate and having a plurality of openings. The dimeni...	03/13/2012
8133792	Method for reducing capacitance variation between capacitors A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connec...	03/13/2012
8129235	Method of fabricating two-step self-aligned contact A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielec...	03/06/2012
8119492	Dissolving precipates in alloy material in capacitor structure A method of fabricating a semiconductor device is provided. The method includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on th...	02/21/2012
8115320	Bond pad structure located over active circuit structure A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and t...	02/14/2012
8115194	Semiconductor device capable of providing identical strains to each channel region of the transistors A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel reg...	02/14/2012
8114773	Cleaning solution, cleaning method and damascene process using the same A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH4F); (d) a chelating agent ...	02/14/2012
8114752	Structure of capacitor set A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connec...	02/14/2012
8101092	Method for controlling ADI-AEI CD difference ratio of openings having different sizes A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidew...	01/24/2012
8096048	Method for fabricating MEMS structure A method for fabricating a MEMS is described as follows. A substrate is provided, including a circuit region and a MEMS region separated from each other. A first metal interconnection structure is formed on the substrate in the circuit region, and simultaneously a f...	01/17/2012
8093118	Semiconductor structure and method of forming the same A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein th...	01/10/2012
8093074	Analysis method for semiconductor device An analysis method for a semiconductor device is described. The semiconductor device having an abnormal region is provided. Thereafter, a focused ion beam microscope analysis process is performed to the abnormal region, wherein the result of the focused ion beam mic...	01/10/2012
8092861	Method of fabricating an ultra dielectric constant (K) dielectric layer A fabrication method of an ultra low-k dielectric layer is provided. A deposition process is performed, under the control of a temperature varying program or a pressure varying program, by reacting a dielectric matrix to form porous low-k dielectric layers with a gr...	01/10/2012
8084289	Method of fabricating image sensor and reworking method thereof A method of fabricating an image sensor device is provided. First, a substrate comprising a pixel array region and a pad region is provided. A patterned metal layer and a first planarization layer having an opening exposing the patterned metal layer in the pad regio...	12/27/2011
8076735	Semiconductor device with trench of various widths A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. ...	12/13/2011
8067281	Method of fabricating complementary metal-oxide-semiconductor (CMOS) Device A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and second type metal-oxide-semiconductor regions. A mask layer is respectiv...	11/29/2011
8063389	Method of performing ion implantation A method of performing an ion implantation is provided. A workpiece is installed in the ion implanter. A wafer is provided in a receiving space within an ion implanter. An ion beam is generated by an ion source of the ion implanter. The bombard of the ion beam is bl...	11/22/2011
8062972	Semiconductor process A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is remove...	11/22/2011
8058733	Self-aligned contact set A self-aligned contact includes a lower contact disposed in a dielectric layer of a substrate and an upper contact disposed in the dielectric layer and directly on the lower contact, and electrically connected to the lower contact. The profile of the upper contact a...	11/15/2011
8058133	Method of fabrication of metal oxide semiconductor field effect transistor A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gat...	11/15/2011
8049279	Semiconductor device and method for fabricating the same A semiconductor device includes a substrate of a first conductivity type, a first doped region of a second conductivity type, at least one second doped region of the first conductivity type, a third doped region of the second conductivity type, a gate structure, and...	11/01/2011
8043919	Method of fabricating semiconductor device A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. The...	10/25/2011
8039330	Method for manufacturing semiconductor device The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer ...	10/18/2011
8039286	Method for fabricating optical device A method for fabricating an optical device includes providing a semiconductor substrate having an element region and a peripheral region. The element region has an element array comprised of semiconductor elements formed therein. The peripheral region has at least a...	10/18/2011
8035097	Phase change memory A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit l...	10/11/2011
8034712	Method of fabricating dual damascene structure A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are pattern...	10/11/2011
8034690	Method of etching oxide layer and nitride layer An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are seque...	10/11/2011
8027144	Capacitor structure A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to ea...	09/27/2011
8021492	Method of cleaning turbo pump and chamber/turbo pump clean process A method of cleaning a turbo pump is described. The turbo pump is coupled with a CVD chamber of depositing a material and thus accumulates the material therein. The method includes using another pump to pump a reactive gas, which can react with the material to form ...	09/20/2011
8019457	Method of controlling result parameter of IC manufacturing procedure A method of controlling a result parameter of an IC manufacturing procedure is described. The value of at least one first variable of a process correlated with the result parameter is acquired, and the difference between the predicted value and the target value of t...	09/13/2011
7989804	Test pattern structure A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interf...	08/02/2011
7982288	Semiconductor device and method of fabricating the same A semiconductor device including a substrate, a high voltage device, a medium voltage device and a low voltage device is provided. The substrate includes a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. The high voltage devi...	07/19/2011
7977769	ESD protection device An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The sec...	07/12/2011
7960838	Interconnect structure An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plu...	06/14/2011
7957827	Method of controlling statuses of wafers A method of controlling statuses of a plurality of wafers is described. A status of a wafer among the wafers is determined. An action related to the status is taken, according to the status determined, to the wafer and/or other wafers to improve a yield or yields th...	06/07/2011

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Assignee: United Microelectronics Corp.