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| Number | Title | Issue Date |
| 7306681 | Method of cleaning a semiconductor substrate A cleaning method and cleaning recipes are disclosed. The present invention relates to a method for cleaning a semiconductor substrate and cleaning recipes. The present invention utilizes a first cleaning solution including diluted hydrofluoric acid and a second cle... | 12/11/2007 |
| 7126150 | Light emitting layer and forming method of the same A light emitting layer including a quantum structure and the forming method of forming the same is provided. The forming method includes several steps. At first, a compound dielectric layer forms, including a dielectric layer and an impure dielectric layer, which co... | 10/24/2006 |
| 7101796 | Method for forming a plane structure A method for forming a plane structure. It comprises the following steps: forms a liquid material with a thicker thickness on a substrate, rotating both the liquid material and the substrate around the axis of the substrate, applying a solvent on the rotating liquid... | 09/05/2006 |
| 7078346 | High density plasma chemical vapor deposition process A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric materia... | 07/18/2006 |
| 7064029 | Semiconductor memory device and method of producing the same A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other vi... | 06/20/2006 |
| 7060547 | Method for forming a junction region of a semiconductor device A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to f... | 06/13/2006 |
| 7056796 | Method for fabricating silicide by heating an epitaxial layer and a metal layer formed thereon A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure ... | 06/06/2006 |
| 7052808 | Transmission mask with differential attenuation to improve ISO-dense proximity An apparatus, system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive open... | 05/30/2006 |
| 7016572 | Optically integrated device The present invention relates to an optically integrated device, and more particularly, to an optically integrated device with low light loss. A color filter is attached to an optical integrator to filter through a portion of the light, and reflect the other portion... | 03/21/2006 |
| 7008882 | Method and structure for the adhesion between dielectric layers A method for forming an adhesion between dielectric layers, it includes forming a first dielectric layer and forming a second dielectric layer having a first portion and a second portion. The first portion is on the first dielectric layer and the second portion is o... | 03/07/2006 |
| 6917076 | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide ... | 07/12/2005 |
| 6894324 | Silicon-on-insulator diodes and ESD protection circuits A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at... | 05/17/2005 |
| 6873505 | Electrostatic discharge protective circuitry equipped with a common discharge line A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one conn... | 03/29/2005 |
| 6861680 | Silicon-on-insulator diodes and ESD protection circuits A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the... | 03/01/2005 |
| 6846697 | Integrated circuit packages and the method for making the same This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and takes advantage of the length between the heat si... | 01/25/2005 |
| 6839126 | Photolithography process with multiple exposures A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. E... | 01/04/2005 |
| 6831013 | Method of forming a dual damascene via by using a metal hard mask layer This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation laye... | 12/14/2004 |
| 6820029 | Method for determining failure rate and selecting best burn-in time A method for determining failure rate and selecting a best burn-in time is disclosed. The method comprises the following steps. First of all, integrate circuits are provided. Then a life-time testing process is performed, wherein a failure rate versus testing time r... | 11/16/2004 |
| 6806160 | Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and inst... | 10/19/2004 |
| 6803310 | Method for forming a plug metal layer Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transporte... | 10/12/2004 |
| 6797457 | Method for improving the resolution of optic lithography A method for improving the resolution of optic lithographic is disclosed. The method includes a step of forming an etched layer on the substrate, an inorganic photoresist layer is spun-on the etched layer, and an atomic layer on the inorganic photoresist layer. Then... | 09/28/2004 |
| 6787461 | Method for forming a plug metal layer Perform an atomic layer deposition (ALD) at least once to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transporte... | 09/07/2004 |
| 6784105 | Simultaneous native oxide removal and metal neutral deposition method A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionall... | 08/31/2004 |
| 6599823 | Method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric A method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric is provided. The present invention includes the steps of forming a trench between each pair of interconnection lines on one level of multi-le... | 07/29/2003 |
| 6583489 | Method for forming interconnect structure with low dielectric constant The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures ar... | 06/24/2003 |
| 6570388 | Transmission line pulse method for measuring electrostatic discharge voltages The present invention relates to a method which introduce a parasitic series resistance for solving electrostatic discharge voltages by using transmission line pulse method and least square error solution method. In present invention, we introduce a paras... | 05/27/2003 |
| 6559004 | Method for forming three dimensional semiconductor structure and three dimensional capacitor A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another diele... | 05/06/2003 |
| 6559476 | Method and structure for measuring bridge induced by mask layout amendment A method for measuring bridge induced by mask layout amendment. Provide a mask with a layout that comprises a conductor line pattern, numerous gate patterns which are connected with conductor line pattern, and numerous contact pattern groups, each contact... | 05/06/2003 |
| 6555485 | Method for fabricating a gate dielectric layer This invention relates to a method for forming a gate dielectric layer, and, more particularly, to a method for treating a base oxide layer by using a remote plasma nitridation procedure and a thermal annealing treatment in turn to form the gate dielectri... | 04/29/2003 |
| 6554002 | Method for removing etching residues A method for removing fluorine-containing etching residues during dual damascene process comprises providing a dual damascene structure having a copper conductor structure therein, a cap layer formed on the copper conductor structure and the dual damascen... | 04/29/2003 |
| 6555893 | Bar circuit for an integrated circuit The present invention provides a bar circuit for reducing cross talk and eddy current of an integrated circuit. The bar circuit comprises a semiconductor substrate with a first conductivity type; a strip of first well with a second conductivity type in th... | 04/29/2003 |
| 6551920 | Semiconductor device and fabrication method thereof A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of ... | 04/22/2003 |
| 6548387 | Method for reducing hole defects in the polysilicon layer A method for reducing hole defects in the polysilicon layer. The method at least includes the following steps. First of all, a semiconductor substrate is provided, a polysilicon layer is formed over the semiconductor substrate. Then, no hole defects botto... | 04/15/2003 |
| 6545350 | Integrated circuit packages and the method for the same This invention relates to a method and a means for packaging integrated circuits, especially relates to a heat sink in the operating integrated circuit packages. The heat sink is bonded on the lead frame by a tap and take advantage of the length between t... | 04/08/2003 |
| 6541749 | Photodetector pixel cell A photodetector pixel cell is proposed by the invention. Herein, the presented pixel cell comprises a diode region and a circuit region, and is enclosed by isolation. Moreover, the doped region is existed inside both regions. The structure of the presente... | 04/01/2003 |
| 6524772 | Method of manufacturing phase grating image sensor A method of manufacturing a phase grating image sensor is disclosed. The method uses conventional photolithography and etching methods to form a plurality of phase grating lenses into the conventional flattening layer on which the conventional micro-lens ... | 02/25/2003 |
| 6524973 | Method for forming low dielectric constant layer The present invention provides a method for forming low dielectric constant layer in a semiconductor device comprising providing the semiconductor device. A dielectric layer is formed on the semiconductor device, which has a constituent of a plurality of ... | 02/25/2003 |
| 6519869 | Method and apparatus for drying semiconductor wafers A method and an apparatus for drying semiconductor wafers by using an IPA drying apparatus. The present invention uses a vapor generator to generate an IPA vapor. The IPA vapor is generated and saved in a closed surrounding and then transferred in a porou... | 02/18/2003 |
| 6521470 | Method of measuring thickness of epitaxial layer A method of measuring the thickness of an epitaxial layer is disclosed. The method is particularly useful in measuring the epitaxial layer with a doping concentration lower than or similar to the substrate on which the epitaxial layer is formed. The metho... | 02/18/2003 |
| 6518164 | Etching process for forming the trench with high aspect ratio First of all, a semiconductor substrate is provided, the semiconductor substrate has a dielectric layer thereon. Then a photoresist layer is formed and defined on the dielectric layer. Next, an etching process is performed by the photoresist layer as an e... | 02/11/2003 |
