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| Number | Title | Issue Date |
| 8114734 | Metal capacitor and method of making the same A method of making a metal capacitor includes the following steps. A dielectric layer having a metal interconnection and a capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the cap... | 02/14/2012 |
| 8105648 | Method for operating a chemical deposition chamber A method for operating a chemical deposition chamber is disclosed. First, a digital liquid flow controller is provided to guide a precursor fluid into a chemical deposition chamber. Then, a pre-cleaning step is performed in the chemical deposition chamber. Later, a ... | 01/31/2012 |
| 7947603 | Chemical-mechanical polishing method A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive... | 05/24/2011 |
| 7932104 | Method for inspecting photoresist pattern A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate ... | 04/26/2011 |
| 7823118 | Computer readable medium having multiple instructions stored in a computer readable device A computer readable medium comprising multiple instructions stored in a computer readable device, upon executing these instructions, a computer performing the following steps: providing a semiconductor layout and a circuit pattern; setting a forbidden area of the ci... | 10/26/2010 |
| 7759244 | Method for fabricating an inductor structure or a dual damascene structure A method for fabricating an inductor structure or a dual damascene structure includes following steps. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric l... | 07/20/2010 |
| 7759202 | Method for forming semiconductor device with gates of different materials A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate diel... | 07/20/2010 |
| 7745889 | Metal oxide semiconductor transistor with Y shape metal gate A metal oxide semiconductor (MOS) transistor with a Y structure metal gate is provided. The MOS transistor includes a substrate, a Y structure metal gate positioned on the substrate, two doping regions disposed in the substrate on two sides of the Y structure metal ... | 06/29/2010 |
| 7745847 | Metal oxide semiconductor transistor The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrat... | 06/29/2010 |
| 7745280 | Metal-insulator-metal capacitor structure A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is dispo... | 06/29/2010 |
| 7741662 | Ultra high voltage MOS transistor device An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region... | 06/22/2010 |
| 7741198 | Method for fabricating a probing pad of an integrated circuit chip A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film.... | 06/22/2010 |
| 7732886 | Pin photodiode structure A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region. ... | 06/08/2010 |
| 7731572 | CMP head A CMP head includes a membrane support and a membrane. The membrane support is disk-shaped, having an origin and a radius R. The membrane support has at least a ventilator disposed in a central region within the range between origin and (⅔) R, and at least a diver... | 06/08/2010 |
| 7728388 | Power semiconductor device A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P+ drain region in the P grade region; a first STI region in the P grade region; a second STI region in... | 06/01/2010 |
| 7723130 | Tooling method for fabricating a semiconductor device and semiconductor devices fabricated thereof A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two... | 05/25/2010 |
| 7719076 | High-voltage MOS transistor device A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first ... | 05/18/2010 |
| 7709908 | High-voltage MOS transistor device A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a firs... | 05/04/2010 |
| 7709275 | Method of forming a pattern for a semiconductor device and method of forming the related MOS transistor A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to fo... | 05/04/2010 |
| 7705666 | Filler circuit cell A filler circuit cell is disclosed. The filler circuit cell includes a decoupled capacitor, a tie low circuit and a tie high circuit. The decoupled capacitor includes a first NMOS transistor and a first PMOS transistor, in which the source/drain of the first NMOS tr... | 04/27/2010 |
| 7700450 | Method for forming MOS transistor A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first... | 04/20/2010 |
| 7700440 | Method of manufacturing a metal-oxide-semiconductor with reduced on-resistance The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering la... | 04/20/2010 |
| 7696606 | Metal structure A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal struc... | 04/13/2010 |
| 7696066 | Method of fabricating intergrated circuit chip A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A number of circuit uni... | 04/13/2010 |
| 7683427 | Laterally diffused metal-oxide-semiconductor device and method of making the same A laterally diffused metal-oxide-semiconductor (LDMOS) device as well as a method of making the same is disclosed. A gate is formed on a semiconductor substrate between a source region and a drain region with one side laterally extending onto a part of a field oxide... | 03/23/2010 |
| 7682932 | Method for fabricating a hybrid orientation substrate A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the firs... | 03/23/2010 |
| 7679070 | Arc chamber for an ion implantation system An arc chamber for an ion implantation system includes an exit aperture positioned at a wall of the arc chamber, filaments respectively positioned at two opposing sides within the arc chamber, and repeller structures respectively positioned at two opposing walls wit... | 03/16/2010 |
| 7678588 | Method for constructing module for optical critical dimension (OCD) and measuring method of module for optical critical dimension using the module An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whe... | 03/16/2010 |
| 7674718 | Method for forming spacers of different sizes A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of t... | 03/09/2010 |
| 7671355 | Method of fabricating a phase change memory and phase change memory The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a botto... | 03/02/2010 |
| 7667566 | Inductor structure An inductor structure comprising a substrate; a plurality of insulation layers on the substrate; a first spiral electric conductive coil positioned in the insulation layers to form an inductor having a first direction of magnetic field; a second spiral electric cond... | 02/23/2010 |
| 7663234 | Package of a semiconductor device with a flexible wiring substrate and method for the same A package of a semiconductor device with a flexible wiring substrate and a method thereof are provided. The package of the semiconductor device includes a semiconductor substrate with at least one pad on a surface thereof, a bump bonded to the pad, an adhesive layer... | 02/16/2010 |
| 7662730 | Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. ... | 02/16/2010 |
| 7662645 | Reworked integrated circuit device and reworking method thereof Reworking method for removing defects on integrated circuit device is disclosed. An integrated circuit is provided, which has a substrate, a conductive material layer formed in the substrate, a dielectric layer formed on the substrate, at least a contact plug embedd... | 02/16/2010 |
| 7659189 | Method for forming fully silicided gate electrode in a semiconductor device A semiconductor MOS device includes a semiconductor substrate; a gate oxide layer disposed on the semiconductor substrate; a fully silicided gate electrode disposed on the gate oxide layer; a composite thin film interposed between the fully silicided gate electrode ... | 02/09/2010 |
| 7656183 | Method to extract gate to source/drain and overlap capacitances and test key structure therefor A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise... | 02/02/2010 |
| 7655987 | Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an u... | 02/02/2010 |
| 7651960 | Chemical vapor deposition method preventing particles forming in chamber Preventing a chemical vapor deposition (CVD) chamber from particle contamination in which a higher low-frequency radio frequency (LFRF) power and longer process time are provided to vacate the chamber and perform a pre-heat process. Following that, a pre-oxide layer... | 01/26/2010 |
| 7649377 | Test structure A wafer level test structure in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by ... | 01/19/2010 |
| 7649268 | Semiconductor wafer A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal struc... | 01/19/2010 |
