Assignee: United Microelectronic Corp.

Location: Hsinchu, TW
No. of patents: 25

Browse patents
Browse applications

Number	Title	Issue Date
7763522	Method of high density plasma gap-filling with minimization of gas phase nucleation A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectri...	07/27/2010
7449741	SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi...	11/11/2008
7435354	Treatment method for surface of photoresist layer and method for forming patterned photoresist layer A treatment method for a surface of a photoresist layer is provided. After forming a patterned photoresist layer over a wafer, a surface treatment step is performed to the photoresist layer by using at least one reaction gas comprising hydrogen bromide or hydrogen i...	10/14/2008
7090350	Optical projection system and method An optical projection system can receive a red light beam, green light beam, and blue light beam. The optical projection system includes a color-combination prism, and the light beams respectively enter the color-combination prism from three surfaces and are combine...	08/15/2006
6960835	Stress-relief layer for semiconductor applications In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias. ...	11/01/2005
6806182	Method for eliminating via resistance shift in organic ILD Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal...	10/19/2004
6646675	Addressable security monitoring system A security monitoring system with addressable capability is provided. This system allows a plurality of video cameras to be connected to the security guard room via a single cable instead of a plurality of dedicated cables, as in the prior art. The securi...	11/11/2003
6621113	Self-aligned shallow trench isolation A method of fabricating a self-aligned shallow trench isolation. A mask layer, two deep trenches and two internal electrodes of a capacitor are sequentially formed on a substrate. Two conductive layers are used to completely fill the two deep trenches. Th...	09/16/2003
6586146	Method of figuring exposure energy A method of figuring an exposure energy. A required exposure energy is calculated according to a critical dimension (CD) of an exposing layer. A first CD deviation is obtained from a layer before the exposing layer. From the first CD deviation, a first en...	07/01/2003
6541782	Electron beam photolithographic process An electron beam photolithographic process for patterning an insulation layer over a substrate. A conductive photoresist layer having a conjugate structure is formed over the insulation layer. An electron beam photolithographic process is conducted using ...	04/01/2003
6455910	Cross guard-ring structure to protect the chip crack in low dielectric constant and copper process A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped via...	09/24/2002
6420077	Contact hole model-based optical proximity correction method A contact hole model-based optical proximity correction method. The method includes building a contact hole model from the database obtained through a series of test patterns each having a plurality of contact holes of different line widths but identical ...	07/16/2002
6413817	Method of forming self-aligned stacked capacitor A method of forming a self-aligned stacked capacitor on a substrate having a first insulation layer thereon. A bit line contact and a first section node contact are formed in the first insulation layer, and then a bit line structure is formed over the fir...	07/02/2002
6180516	Method of fabricating a dual damascene structure The present invention provides an improved method of forming a dual damascene structure. Patterns of a metallic trench and a via hole are formed by using the photolithography process twice. After the first etching step of the dielectric layer the first ph...	01/30/2001
6171951	Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening A dual damascene manufacturing method includes utilizing a low dielectric constant material to form the dielectric layers and to prevent current due to the reduced line width. An implanting step is performed on the dielectric layers to reduce the incohere...	01/09/2001
6169035	Method of local oxidation using etchant and oxidizer A LOCOS method uses a reagent mixed of etchant and oxidizer to simultaneously perform the step of forming the FOX layer and the step of removing a mask layer of the conventional LOCOS method. The applied temperature is about 950-1150° C. The etchant. suc...	01/02/2001
6124638	Semiconductor device and a method of manufacturing the same A polycide wiring layer constituted by a polysilicon film and a silicide film is used as a bit line of a DRAM. When a memory cell region having an n-type impurity diffusion layer and a peripheral circuit region having a p-type impurity diffusion layer are...	09/26/2000
6066886	Semiconductor wafer in which redundant memory portion is shared by two neighboring semiconductor memory portions and is connected to the semiconductor memory portions Redundant memory portions having redundant memory cells for relieving malfunctioning normal memory cells are arranged among the semiconductor memory portions that neighbor each other in the row direction and in the column direction on a semiconductor wafe...	05/23/2000
6048776	Semiconductor device and a method of fabricating the same A method of fabricating a semiconductor device, comprises the steps of forming a trench in a semiconductor substrate by using a selective etching process; forming an insulating layer at least on the inner surface of the trench; forming a film containing s...	04/11/2000
6026012	Dual port random access memory A dual port random access memory (RAM). The dual port random access memory includes four N-MOS transistors and four P-MOS transistors. Both the N-MOS and the P-MOS transistors are used as pass gates. More specifically, two N-MOS transistors are used as pa...	02/15/2000
5936279	Method of fabricating self-align contact window with silicon nitride side wall A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first s...	08/10/1999
5712185	Method for forming shallow trench isolation A method for forming shallow trench isolation without a recessed edge problem is disclosed. The present invention comprises forming a pad oxide layer on a substrate. Next, a silicon nitride layer is formed on the pad oxide, and a sacrificial layer is form...	01/27/1998
5661479	Oversampling modulation in a D/A converter using a combination of feedforward/feedback coefficients and shift registers A high-order oversampling modulation apparatus is disclosed herein. The present invention implements a high-order oversampling modulation apparatus by use of a plurality of shift registers in response to clock signals provided with a frequency higher than...	08/26/1997
5429973	Trench buried-bit line mask ROM process A method for fabricating a trench buried-bit line mask ROM includes the steps: firstly, longitudinally coating a plurality of spaced photo-resist strips on a silicon well surface thus dividing the silicon well surface into a plurality longitudinally space...	07/04/1995
5374583	Technology for local oxidation of silicon A new method of local oxidation by means of forming a plurality of silicon trenches is described. Portions of the insulating layer over the surface of a silicon substrate not covered by a mask pattern are etched through exposing the portion of the silicon...	12/20/1994

PatentStorm

Bizarre Patents

PatentStorm News

Assignee: United Microelectronic Corp.