Bizarre Patents
A simulation environment for the sport of boxing utilizing a robotic machine interface system which carries a person.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8112572 | Apparatus for swapping high-speed multimedia signals An apparatus for swapping output high-speed multimedia signals. In one embodiment the apparatus comprises a plurality of inputs coupled to a multimedia transmitter; a plurality of outputs coupled to a plurality of pins of a multimedia interface connector; and a cont... | 02/07/2012 |
| 8098690 | System and method for transferring high-definition multimedia signals over four twisted-pairs A system and method for transferring high-definition multimedia signals over four twisted-pairs. The system includes a multimedia source for transmitting multimedia data and source-to-sink management data to a multimedia sink over a first channel, a second channel a... | 01/17/2012 |
| 7873938 | Method for constructing a variable bitwidth video processor A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instan... | 01/18/2011 |
| 7714565 | Methods and apparatus for testing delay locked loops and clock skew According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay in... | 05/11/2010 |
| 7680943 | Methods and apparatus for implementing multiple types of network tunneling in a uniform manner A uniform method for implementing multiple tunneling protocols in a switch or router is disclosed. The method is based on the realization that although the tunneling protocols are very different, they do share a similar overall structure which can be exploited to cr... | 03/16/2010 |
| 7672315 | Methods and apparatus for deskewing VCAT/LCAS members Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans th... | 03/02/2010 |
| 7653072 | Overcoming access latency inefficiency in memories for packet switched networks A method buffering packets in a packet switching network (FIG. 5) includes receiving a packet from the network; splitting the packet into a plurality of PDUs; stripping at least some of the PDUs over a plurality of memory banks; (18) retrieving the PDU... | 01/26/2010 |
| 7649843 | Methods and apparatus for controlling the flow of multiple signal sources over a single full duplex ethernet link Methods for providing flow control of signal streams over a single full duplex ETHERNET link include receiving multiple data streams over a single ETHERNET link, associating a buffer with each data stream, putting received data into the appropriate buffer, monitorin... | 01/19/2010 |
| 7630397 | Efficient scalable implementation of VCAT/LCAS for SDH and PDH signals An apparatus for implementing VCAT in both SDH and PDH signals includes an SDH VCAT mapper coupled to a first telecom bus and a plurality of PDH units coupled to the first telecom bus and a second telecom bus. The PDH units read SDH VCAT bytes from the first telecom... | 12/08/2009 |
| 7613213 | Time multiplexed SONET line processing Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and ... | 11/03/2009 |
| 7577089 | Methods and apparatus for fast ETHERNET link switchover in the event of a link failure An apparatus for fast failure switch over in an ETHERNET switch includes redundant switch (trunk) ports (a main and a backup) and hardware and software logic for redirecting traffic to the backup port when the main port (or the link associated with it) fails. The sw... | 08/18/2009 |
| 7558287 | Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT) Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardwa... | 07/07/2009 |
| 7433871 | Efficient ipv4/ipv6 best matching prefix method and apparatus The present invention provides a data-structure to store a search database and provides techniques to build this datastructure given a list of prefixes (P) and to search this database efficiently for a best matching prefix for an address D. The data-structure can be... | 10/07/2008 |
| 7430201 | Methods and apparatus for accessing full bandwidth in an asynchronous data transfer and source traffic control system Methods for accessing full bandwidth in an asynchronous data transfer and source traffic control system include permitting some bus users (e.g. networks cards) to access both odd and even frames while permitting other bus users (e.g. subscriber line cards) to access... | 09/30/2008 |
| 7401333 | Array of parallel programmable processing engines and deterministic method of operating the same The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects e... | 07/15/2008 |
| 7355380 | Methods and apparatus for testing delay locked loops and clock skew According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay in... | 04/08/2008 |
| 7349444 | SONET/SDH SPE/virtual container retiming with adaptive dual pointer leak rate computation Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the r... | 03/25/2008 |
| 7349405 | Method and apparatus for fair queueing of data packets A packet scheduling method and apparatus is described for enqueuing incoming data packets in sessions, and for storing the sessions in sequential order in service-groups. Each service-group is assigned a nominal service-interval in which time a data packet is to be ... | 03/25/2008 |
| 7342885 | Method and apparatus for implementing a backpressure mechanism in an asynchronous data transfer and source traffic control system Methods for implementing a backpressure mechanism in an asynchronous data transfer and source traffic control system include detecting when a bus user is experiencing congestion and preventing other bus users from sending cells over the bus. According to a first emb... | 03/11/2008 |
| 7313151 | Extendible asynchronous and synchronous interface bus for broadband access Apparatus for simultaneously transferring synchronous and asynchronous signals among broadband access devices includes a data bus, a clock bus, and a plurality of control lines which are used to indicate the type of data being carried on the bus. According to the me... | 12/25/2007 |
| 7274657 | Methods and apparatus for providing redundancy in an asynchronous data transfer and source traffic control system Methods and apparatus for providing redundancy in an asynchronous data transfer and source traffic control system include configuring a primary client and a backup client with the same receive address but different transmit addresses. This allows both clients to rec... | 09/25/2007 |
| 7260767 | Methods and apparatus for error correction of transparent GFP (Generic Framing Procedure) superblocks Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In ... | 08/21/2007 |
| 7239651 | Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same A SONET demapper includes three desynchronizers, each of which includes a RAM-based, shared digital phase locked loop, shared elastic storage, and twenty-eight divide-by 33/34/44/45 counters. Unlike a conventional desynchronizer which uses separate FIFOs for each of... | 07/03/2007 |
| 7177328 | Cross-connect switch for synchronous network A cross-connect switch (1000) is adapted for a plurality of input channels in a synchronous network. Each input channel has a pointer processor (800) including a pointer interpreter (802), an elastic store buffer (804), and a pointer gene... | 02/13/2007 |
| 7072292 | Methods and apparatus for supporting multiple Utopia masters on the same Utopia bus Methods and apparatus for supporting multiple UTOPIA bus masters on a single UTOPIA bus include coupling two UTOPIA bus masters via three signal lines (Ready, Request, and Grant), designating one of the masters a primary master and the other a secondary master, and ... | 07/04/2006 |
| 7061935 | Method and apparatus for arbitrating bandwidth in a communications switch A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the p... | 06/13/2006 |
| 7031256 | Methods and apparatus for implementing LCAS ( link capacity adjustment scheme) sinking with rate based flow control Methods for extracting packetized data from a SONET/SDH signal include processing the signal to produce a deskewed data stream; demapping the data stream to produce a stream of packets; and temporarily storing the packets in a packet buffer, wherein the demapping is... | 04/18/2006 |
| 7020158 | Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames The methods of the invention include providing a state machine on chip with a SONET/SDH mapper and providing means whereby a plurality of members of a VCG can share the same state machine. The apparatus of the invention preferably includes a “smart” time wheel f... | 03/28/2006 |
| 6965612 | Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames include providing a state machine on chip with a SONET/SDH mapper and providing means whereby a plurality of members of a VCG can share ... | 11/15/2005 |
| 6822939 | Method and apparatus for guaranteeing a minimum cell rate (MCR) for asynchronous transfer mode (ATM) traffic queues An apparatus for guaranteeing MCR in an ATM device includes at least one queue for each service category, a scheduler for dequeuing cells from the queues, a queue status block for indicating which queues are empty, and an MCR service block. The MCR service block inc... | 11/23/2004 |
| 6765867 | Method and apparatus for avoiding head of line blocking in an ATM (asynchronous transfer mode) device An apparatus for avoiding head of line blocking in an ATM device includes a scheduler, at least one multicast queue, at least one unicast queue, a multicast session table, a multicast timer, and a problem PHY vector. The methods of the invention include alternate sc... | 07/20/2004 |
| 6754805 | Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration An improved mechanism for performing different types of digital signal processing functions, including correlation, sorting, and filtering operations. The mechanism includes a plurality of computational cells which can be dynamically configured (and reconfigured) in... | 06/22/2004 |
| 6646983 | Network switch which supports TDM, ATM, and variable length packet traffic and includes automatic fault/congestion correction A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodi... | 11/11/2003 |
| 6636511 | Method of multicasting data through a communications switch A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodi... | 10/21/2003 |
| 6636515 | Method for switching ATM, TDM, and packet data through a single communications switch A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodi... | 10/21/2003 |
| 6631130 | Method and apparatus for switching ATM, TDM, and packet data through a single communications switch while maintaining TDM timing A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodi... | 10/07/2003 |
| 6539023 | Methods and apparatus for handling maintenance messages in extended superframe T1 telephone circuits An apparatus for handling back-to-back maintenance messages in extended superframe t1 telephone circuits includes a FIFO, a byte counter, and a message length register. According toga method of the invention, when messages are placed in the. FIFO, the byt... | 03/25/2003 |
| 6463111 | Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload The desynchronizer of the present invention includes two FIFOs. The first FIFO has two address counters (write and read), an intermediate count register, circuitry for calculating the difference between the write and intermediate counts and the intermedia... | 10/08/2002 |
| 6456595 | Alarm indication signal detection in the presence of special line codes in DS1 (T1) telephone circuits A method and apparatus for reliably detecting both AIS and AIS-CI signals in the presence of a bit error ratio up to 1×10-3 includes an AIS detector having an AIS indication output, a CI detector having a CI indication output, and a two signal... | 09/24/2002 |
| 6356561 | Method and apparatus for the fair and efficient transfer of variable length packets using fixed length segments A method for the fair and efficient transfer of variable length packets using fixed length "segments" utilizes a modified UTOPIA interface with three additional signals added, i.e. start of packet (SOP), end of packet (EOP), and most significant byte (MSB... | 03/12/2002 |
