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| Number | Title | Issue Date |
| 7562233 | Adaptive control of operating and body bias voltages Adaptive control of operating and body bias voltages. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The ... | 07/14/2009 |
| 7509504 | Systems and methods for control of integrated circuits comprising body biasing systems Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage i... | 03/24/2009 |
| 7498846 | Power efficient multiplexer A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for invert... | 03/03/2009 |
| 7495497 | Temperature compensated integrated circuits A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation. ... | 02/24/2009 |
| 7496868 | Method and system for automated schematic diagram conversion to support semiconductor body bias designs A computer implemented method and system for converting schematic diagrams. The method includes accessing a first set of schematic diagrams, wherein the schematic diagrams represent an integrated circuit design to be realized in physical form. A plurality of a first... | 02/24/2009 |
| 7496727 | Secure memory access system and method A secure memory access system and method for providing secure access to Hyper Management Mode memory ranges is presented. ... | 02/24/2009 |
| 7495466 | Triple latch flip flop system and method A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down no... | 02/24/2009 |
| 7478226 | Processing bypass directory tracking system and method A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass d... | 01/13/2009 |
| 7472033 | Apparatus for controlling semiconductor chip characteristics Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating character... | 12/30/2008 |
| 7463050 | System and method for controlling temperature during burn-in Systems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to control junction temperature (e.g., temperature measured at the device und... | 12/09/2008 |
| 7456628 | System and method for measuring negative bias thermal instability with a ring oscillator An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT), a first ring oscillator, a second DUT and a second ring oscillator. The first DUT is biased such that interface traps are generated during a ... | 11/25/2008 |
| 7451300 | Explicit control of speculation Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled for processor registers and other memories private to a microprocess... | 11/11/2008 |
| 7444471 | Method and system for using external storage to amortize CPU cycle utilization A method and system for using external storage to amortize CPU cycle utilization, wherein translated instructions are stored in a storage medium and subsequently accessed on a subsequent execution of a non-native application in order to amortize CPU cycles used in g... | 10/28/2008 |
| 7414485 | Circuits, systems and methods relating to dynamic ring oscillators A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in se... | 08/19/2008 |
| 7405597 | Advanced repeater with duty cycle adjustment An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selec... | 07/29/2008 |
| 7404181 | Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the p... | 07/22/2008 |
| 7404093 | System and method for saving and restoring a processor state without executing any instructions from a first instruction set A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program executio... | 07/22/2008 |
| 7388260 | Structure for spanning gap in body-bias voltage routing structure Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire. ... | 06/17/2008 |
| 7380098 | Method and system for caching attribute data for matching attributes with physical addresses A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical addr... | 05/27/2008 |
| 7380096 | System and method for identifying TLB entries associated with a physical address of a specified range A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB e... | 05/27/2008 |
| 7376798 | Memory management methods and systems that support cache consistency Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In res... | 05/20/2008 |
| 7375556 | Advanced repeater utilizing signal distribution delay An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop ... | 05/20/2008 |
| 7362165 | Servo loop for well bias voltage source A servo loop for a charge pump including comparator. A variable resistor and comparator are in series and couple the output of the charge pump to an enable input. A current source/sink coupled to the variable resistor provide a first input voltage to the comparator,... | 04/22/2008 |
| 7343473 | System and method for translating non-native instructions to native instructions for processing on a host processor A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The s... | 03/11/2008 |
| 7337439 | Method for increasing the speed of speculative execution A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been sele... | 02/26/2008 |
| 7337307 | Exception handling with inserted status check command accommodating floating point instruction forward move across branch A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined instructions by moving a floating point instruction from after a bra... | 02/26/2008 |
| 7336103 | Stacked inverter delay chain Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power charac... | 02/26/2008 |
| 7336092 | Closed loop feedback control of integrated circuits Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An op... | 02/26/2008 |
| 7336090 | Frequency specific closed loop feedback control of integrated circuits Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indi... | 02/26/2008 |
| 7332763 | Selective coupling of voltage feeds for body bias voltage in an integrated circuit device An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupl... | 02/19/2008 |
| 7334198 | Software controlled transistor body bias Software controlled body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasin... | 02/19/2008 |
| 7334173 | Method and system for protecting processors from unauthorized debug access A method for securing a scan test architecture by performing an authentication operation to authorize use of a protected scan chain. ... | 02/19/2008 |
| 7332931 | Leakage efficient anti-glitch filter with variable delay stages A leakage efficient anti-glitch filter with variable delay stages. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter with variable delay stages comprises a plurality of variable delay stages and a coincidence dete... | 02/19/2008 |
| 7331041 | Method of changing modes of code generation A method for determining a process to use for converting instructions in a target instruction set to instructions in a host instructions set including the steps of executing code morphing software including an interpreter and a translator to generate host instructio... | 02/12/2008 |
| 7330080 | Ring based impedance control of an output driver One embodiment in accordance with the invention is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the in... | 02/12/2008 |
| 7330054 | Leakage efficient anti-glitch filter A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter comprises a delay element and a coincidence detector element for detecting coincidence of an input signal to the delay elem... | 02/12/2008 |
| 7329928 | Voltage compensated integrated circuits A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation. ... | 02/12/2008 |
| 7330959 | Use of MTRR and page attribute table to support multiple byte order formats in a computer system Computer technology supports multiple byte order formats, separately or simultaneously. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. The PAT has a plurality of entries. Each entry indicates a memo... | 02/12/2008 |
| 7323367 | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described. ... | 01/29/2008 |
| 7315178 | System and method for measuring negative bias thermal instability with a ring oscillator An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT) module coupled to a first ring oscillator module and a second DUT module coupled to a second ring oscillator module. The first DUT module is b... | 01/01/2008 |
