Assignee: Tilera Corporation

Location: Westborough, MA
No. of patents: 34

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Number	Title	Issue Date
8181168	Memory access assignment for parallel processing architectures A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being relate...	05/15/2012
8151088	Configuring routing in mesh networks A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimension...	04/03/2012
8127111	Managing data provided to switches in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over da...	02/28/2012
8112581	Caching in multicore and multiprocessor architectures A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more direc...	02/07/2012
8086554	Pattern matching in a multiprocessor environment Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible b...	12/27/2011
8065259	Pattern matching in a multiprocessor environment Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible b...	11/22/2011
8050256	Configuring routing in mesh networks A processor includes a plurality of processor tiles, each tile including a processor core, and an interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensi...	11/01/2011
8045546	Configuring routing in mesh networks A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. An extension network connects input/output ports of the ...	10/25/2011
8018849	Flow control in a parallel processing environment The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switche...	09/13/2011
7987321	Caching in multicore and multiprocessor architectures A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which e...	07/26/2011
7882307	Managing cache memory in a parallel processing environment An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for...	02/01/2011
7877401	Pattern matching A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the ...	01/25/2011
7853774	Managing buffer storage in a parallel processing environment An integrated circuit including a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data words over data paths from other tiles to the processor and to switches of other tiles; and memory coupled to the switch to ...	12/14/2010
7853755	Caching in multicore and multiprocessor architectures A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which e...	12/14/2010
7853754	Caching in multicore and multiprocessor architectures A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more direc...	12/14/2010
7853752	Caching in multicore and multiprocessor architectures A multicore processor includes a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more input/...	12/14/2010
7814242	Managing data flows in a parallel processing environment An integrated circuit includes a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; a receive buffer to store the data received...	10/12/2010
7805577	Managing memory access in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ...	09/28/2010
7805575	Caching in multicore and multiprocessor architectures A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some ...	09/28/2010
7805392	Pattern matching in a multiprocessor environment with finite state automaton transitions based on an order of vectors in a state transition table Pattern matching in a plurality of interconnected processing engines includes: accepting a stream of input sequences over an interface and storing the input sequences; storing instructions for matching an input sequence to one or more patterns in memory accessible b...	09/28/2010
7793074	Directing data in a parallel processing environment An apparatus comprises a plurality of processor cores, and an interconnection network to route data among the processor cores based on destination information in the data. The processor cores are configured to forward the data to a final destination if the destinati...	09/07/2010
7774579	Protection in a parallel processing environment using access information associated with each switch to prevent data from being forwarded outside a plurality of tiles An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ...	08/10/2010
7774553	Caching in multicore and multiprocessor architectures A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; and a plurality of memory interfaces providing memory access paths from the cache memories to a main memory, at least some ...	08/10/2010
7734894	Managing data forwarded between processors in a parallel processing environment based on operations associated with instructions issued by the processors An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over da...	06/08/2010
7673206	Method and system for routing scan chains in an array of processor resources The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column i...	03/02/2010
7668979	Buffering data in a parallel processing environment An integrated circuit includes a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; a first buffer that stores data from the sw...	02/23/2010
7636835	Coupling data in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ...	12/22/2009
7624248	Managing memory in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises: a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received fro...	11/24/2009
7620791	Mapping memory in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ...	11/17/2009
7577820	Managing data in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over da...	08/18/2009
7552241	Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip The present invention relates to a method and system for managing I/O interfaces with an array of multicore processor resources in a semiconductor chip. The I/O interfaces are connected to the processor resources through an I/O shim. An I/O interface sends a datafra...	06/23/2009
7539845	Coupling integrated circuits in a parallel processing environment An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received ...	05/26/2009
7461236	Transferring data in a parallel processing environment An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles according to a switch instruction indica...	12/02/2008
7461210	Managing set associative cache memory according to entry type Managing memory includes: mediating access to a first memory as a cache for a second memory; and associating one of a plurality of entry types with entries in the cache. Data from the second memory associated with a first type is not allowed to evict a cache entry a...	12/02/2008

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Assignee: Tilera Corporation