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| Number | Title | Issue Date |
| 4687989 | CMOS powerless rom code mask option select An integrated circuit having an option between two or more configurations and also using a patterned ion-implant for impressing data (such as a ROM section of the circuit) may advantageously perform the option-specification simultaneously with the ROM; us... | 08/18/1987 |
| 4685128 | Method and network for transmitting addressed signal samples from any network input to an addressed network output An address (n) is associated with a sort element (30) so that input signals are compared with each other, or with the address (n) in the case of a null input (N). Several elements (30) are interconnected to provide unique signal routing from any input to ... | 08/04/1987 |
| 4685086 | Memory cell leakage detection circuit A circuit for detecting a short circuit in a SRAM memory cell (10) includes means for connecting the nodes (21, 23) of the memory cell to the gates of a pair of pulldown transistors (66, 68). The pulldown transistors perform a level-shifting function to p... | 08/04/1987 |
| 4679300 | Method of making a trench capacitor and dram memory cell A method of making a trench capacitor employs an N-type switchable plate formed in a P-type substrate for holding charge at either zero volts or a positive TC voltage and a P-type ground plate that fills in a trench around a memory cell, so that P-type do... | 07/14/1987 |
| 4677593 | Low active-power address buffer A buffer circuit accepting TTL input levels and generating logic-level signals incorporates means to reduce the power consumption in the circuit in the active phase as well as the inactive phase, without imposing additional restrictions on the user.... | 06/30/1987 |
| 4669063 | Sense amplifier for a dynamic RAM A single ended sense amplifier (10) receives a bit line signal (16) at the gate of a detector MOS transistor (36). The source of the detector transistor (36) is connected to a reference voltage (24) which is adjusted prior to each memory cycle to make the... | 05/26/1987 |
| 4661926 | Bit line gain circuit for read only memory A ROM memory circuit featuring a bit line gain circuit to the output thereof, effective for establishing isolation of bit and output lines, reduction of bit line voltage swing, VREF level tracking and bit line select circuitry performing a logical OR betw... | 04/28/1987 |
| 4649540 | Error-correcting circuit having a reduced syndrome word An error-correction circuit for correcting up to one error in an M-bit data field having the conventional number K parity bits associated with it uses a syndrome word having K-1 bits. The data elements are ordered sequentially and the K-1 bit syndrome wor... | 03/10/1987 |
| 4649301 | Multiple-input sense amplifier with two CMOS differential stages driving a high-gain stage A multiple input differential sense amplifier including a pair of signal inputs and comprising a bank of n-channel MOS transistors for receiving said multiple inputs for connection to one of said signal inputs. The other of said signal inputs can be provi... | 03/10/1987 |
