Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 7974005 | Display screen for use in front projectors A screen for use in image presentations comprises an array of transmissive elongated prisms. The screen is capable of delivering incident light, having an incident angle within a specific incident angle range, to the viewing area, while preventing ambient light, hav... | 07/05/2011 |
| 7973557 | IC having programmable digital logic cells An integrated circuit (IC) includes at least one programmable digital logic cell that includes first dedicated digital logic cell having a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor configured to perform at least... | 07/05/2011 |
| 7973535 | Methods and apparatus to manage ground fault conditions with a single coil A ground fault detection device includes a sense coil including a primary winding and a secondary winding to detect current in a line conductor and a neutral conductor. It also includes a capacitor in parallel with the secondary winding and a virtual inductor to for... | 07/05/2011 |
| 7973523 | Reverse current sensing regulator system and method A reverse current sensing (RCS) regulator system and method is provided. One embodiment of the invention includes a RCS regulator system. The system comprises a RCS comparator that monitors a drain voltage of a LS FET and is configured to switch states at a zero cro... | 07/05/2011 |
| 7973416 | Thru silicon enabled die stacking scheme A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a ba... | 07/05/2011 |
| 7972905 | Packaged electronic device having metal comprising self-healing die attach material A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece and an IC die. The die attach adhesive precursor includes metal particles, a first plurality of first microc... | 07/05/2011 |
| 7972020 | Apparatus and method for reducing speckle in display of images An apparatus and method of reducing speckle in projection of images is provided that includes the elements or features of producing a first image and displacing the first image to produce a second image that will reduce speckle relating to the first image when the f... | 07/05/2011 |
| 7972004 | System and method for uniform light generation A system and method for uniform light generation in projection display systems. An illumination source comprises a light source to produce colored light, and a scrolling optics unit optically coupled to the light source, the scrolling optics unit configured to creat... | 07/05/2011 |
| 7972001 | Projection illumination device and method for projection visual display system using multiple controlled light emitters having individual wavelengths A method for compensating for a shift in color in a light source and a system of color illumination for a projection visual display (PVD) system. In one embodiment, the method includes: (1) field sequentially operating an array of emitters to generate a sequence of ... | 07/05/2011 |
| 7971351 | Method of manufacturing a semiconductor device The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural ... | 07/05/2011 |
| 7970230 | Image processing with minimization of ringing artifacts and noise A method of reducing ringing artifacts in image data that has been filtered with a high frequency emphasis filter. For each filtered data value, a local variance is calculated from data values at neighboring filter taps. This variance is compared to a threshold, and... | 06/28/2011 |
| 7969334 | Apparatus for correcting setting error in an MDAC amplifier Multiplying digital-to-analog converters (MDACs), which are generally employed in pipelined analog-to-digital converters (ADCs), can have a settling error associated with the MDAC amplifier. Here, a circuit is provided that includes additional amplifiers and a capac... | 06/28/2011 |
| 7969219 | Wide range delay cell A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) prov... | 06/28/2011 |
| 7968950 | Semiconductor device having improved gate electrode placement and decreased area design A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located within a semiconductor substrate. A gate oxide is located between the gate electrode and the active regio... | 06/28/2011 |
| 7968878 | Electrical test structure to detect stress induced defects using diodes A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array... | 06/28/2011 |
| 7968415 | Transistor with reduced short channel effects and method A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using... | 06/28/2011 |
| RE42494 | Preventing drain to body forward bias in a MOS transistor A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V | 06/28/2011 |
| 7966528 | Watchdog mechanism with fault escalation A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx esc... | 06/21/2011 |
| 7966183 | Multiplying confidence scores for utterance verification in a mobile telephone Automatic speech recognition verification using a combination of two or more confidence scores based on UV features which reuse computations of the original recognition. ... | 06/21/2011 |
| 7965797 | Method, system and apparatus for generating constant amplitude zero autocorrelation sequences A method, system and apparatus for generating a constant amplitude zero autocorrelation (CAZAC) sequence to be transmitted on a wireless communication channel between a user equipment and a base station within a cellular communication network includes iteratively ca... | 06/21/2011 |
| 7965657 | Sounding reference signal cell specific sub-frame configuration A method of wireless communication including a plurality of fixed basestations and a plurality of mobile user equipment with each basestation transmitting to any user equipment within a corresponding cell a sounding reference signal sub-frame configuration indicatin... | 06/21/2011 |
| 7965139 | Amplifier offset and noise reduction in a multistage system Conventional multistage amplifiers oftentimes employ trim circuits or highly matched components to combat noise and offset contributions. Having trim circuitry or highly matched components increases the overall size, cost, and power consumption, so it is desirable t... | 06/21/2011 |
| 7965100 | Transmitter with internal compensation for variance in differential data line impedance In at least some embodiments, an electronic device includes a first data endpoint and differential data transceiver coupled to the first data endpoint. The differential transceiver provides a communication interface between the first data endpoint and a second data ... | 06/21/2011 |
| 7965071 | DC-DC boost converter A DC-DC boost converter is provided that generally maintains discontinuous mode operation in a generally efficient manner. To accomplish this, a clamp generator, comparator, logic gates, a flip-flop, and counter are employed. These components generally operate toget... | 06/21/2011 |
| 7965067 | Dynamic compensation for a pre-regulated charge pump An apparatus is provided. The apparatus comprises an error amplifier that amplifies the difference between a reference voltage and a feedback voltage, a first variable impedance circuit coupled to the error amplifier that receives a control voltage from the error am... | 06/21/2011 |
| 7964919 | Thin film resistors integrated at two different metal single die An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A ... | 06/21/2011 |
| 7962872 | Timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy An aspect of the present invention provides for timing analysis when integrating multiple circuit blocks while balancing resource requirements and accuracy. In an embodiment, an optimized model for a circuit block is created by combining information provided by two ... | 06/14/2011 |
| 7962817 | IEEE 1149.1 and P1500 test interfaces combined circuits and processes In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP b... | 06/14/2011 |
| 7962815 | Tap demultiplexer with select and select one outputs for HTML An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hie... | 06/14/2011 |
| 7962813 | 1149.1 tap linking modules IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, ... | 06/14/2011 |
| 7962183 | Apparatus for and method of managing peak current consumption of multiple subsystems in a mobile handset A novel and useful mechanism for regulating and managing the peak current consumption of the subsystems in a mobile handset device. The mechanism of the present invention is operative to limit the current consumption at any point in time to a predetermined level tha... | 06/14/2011 |
| 7961892 | Apparatus and method for monitoring speaker cone displacement in an audio speaker An apparatus for monitoring speaker cone displacement in an audio speaker includes: (a) an electromagnetic coil structure; (b) a ferrous core structure; the ferrous core structure and the electromagnetic coil structure being mounted with the speaker to effect variab... | 06/14/2011 |
| 7961826 | Parameterized sphere detector and methods of using the same A Multiple-input Multiple-Output (MIMO) receiver is provided. The MIMO receiver comprises a parameterized sphere detector having two search modes. During a first search mode, the parameterized sphere detector enumerates a number of best candidate vectors up to a fix... | 06/14/2011 |
| 7961774 | Multipath interference-resistant receivers for closed-loop transmit diversity (CLTD) in code-division multiple access (CDMA) systems System and method for providing interference resistance in communications systems using closed-loop transmit diversity (CLTD). A preferred embodiment comprises: at a receiver, computing a CLTD weighting vector from a received signal, providing the CLTD weighting vec... | 06/14/2011 |
| 7961672 | CQI feedback for OFDMA systems Embodiments of a feedback generator and decoder and methods of operating the feedback generator and decoder are presented. In one embodiment, the feedback generator includes a CQI compression module configured to provide a compressed CQI for the user equipment corre... | 06/14/2011 |
| 7961575 | Automatic DTS CD Versus CD-DA detection within a file system-based device A method of detection is described to be used in file system-based player devices to determine the type of compact disk that has been inserted into a player. The method automatically distinguishes between the DTS-CD format and standard audio CDs. The method allows t... | 06/14/2011 |
| 7961418 | Resistivity sense bias circuits and methods of operating the same Resistivity sense bias circuits are described herein. An example resistivity sense bias circuit for use with a magnetoresistive read head includes a current biasing portion configured to provide a bias current across the magnetoresistive read head thereby establishi... | 06/14/2011 |
| 7961376 | Reducing adherence in a MEMS device In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly from the substrate. The MEMS comprises structures and corresponding landing pads. Dibs are disposed outwardly... | 06/14/2011 |
| 7961123 | Time-interleaved analog-to-digital converter A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least ... | 06/14/2011 |
| 7960840 | Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side ... | 06/14/2011 |