Assignee: Texas Instruments-Acer Incorporated

Location: Hsinchu, TW
No. of patents: 32

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Number	Title	Issue Date
6649308	Ultra-short channel NMOSFETS with self-aligned silicide contact The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are...	11/18/2003
6548362	Method of forming MOSFET with buried contact and air-gap gate structure A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations...	04/15/2003
6265259	Method to fabricate deep sub-μm CMOSFETs The method of the present invention is to fabricate a CMOS device without boron penetration. Firstly, a gate oxide layer is formed on a semiconductor substrate. A first silicon layer is formed upon the gate oxide layer. Thereafter, a second silicon layer ...	07/24/2001
6211016	Method for forming high density nonvolatile memories with high capacitive-coupling ratio A method for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the t...	04/03/2001
6211002	CMOS process for forming planarized twin wells This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as a mask. A thick ...	04/03/2001
6207999	Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage The present invention provides a mask ROM memory to minimize band-to-band leakage. The substrate includes a normal NMOS device region and a NMOS cell region for coding. An isolation region is formed between the normal NMOS device region and the NMOS cell ...	03/27/2001
6207505	Method for forming high density nonvolatile memories with high capacitive-coupling ratio A method for fabricating a high-speed and high-density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the t...	03/27/2001
6204517	Single electron transistor memory array A structure of a single-electron-transistor memory array is disclosed in the present invention. A substrate is provided. A buried oxide layer is on the substrate. A plurality of silicon wires are arranged on the buried oxide layer, wherein each of the sil...	03/20/2001
6180988	Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure A MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. ...	01/30/2001
6137131	Dram cell with a multiple mushroom-shaped capacitor The capacitor includes a first storage node formed over a semiconductor wafer. The first storage node has a plurality of mushroom-shape structures. The plurality of mushroom-shape structures are randomly arranged on the first storage node to increase the ...	10/24/2000
6117731	Method of forming high capacitive-coupling ratio and high speed flash memories with a textured tunnel oxide The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers are formed on the side walls of the gate structure. Then, source/drain...	09/12/2000
6114201	Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a multiple...	09/05/2000
6107126	Method to form different threshold NMOSFETS for read only memory devices A method for fabricating a Read Only Memory, (ROM), cell on a semiconductor substrate with device region and programmable cell region. The method includes the followed step. A plurality of field oxide regions is formed on the semiconductor substrate. A P-...	08/22/2000
6069044	Process to fabricate ultra-short channel nMOSFETS with self-aligned silicide contact The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped poly...	05/30/2000
6064085	DRAM cell with a multiple fin-shaped structure capacitor The present invention discloses a novel multiple fin-shaped capacitor for use in semiconductor memories. The capacitor has a plurality of horizontal fins and a crown shape. The capacitor structure comprises a bottom storage electrode. The bottom storage e...	05/16/2000
6043124	Method for forming high density nonvolatile memories with high capacitive-coupling ratio The present invention proposes a method for fabricating a high speed and high density nonvolatile memory cell. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposi...	03/28/2000
6020230	Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion The method in the present invention is proposed for forming trench isolation in a semiconductor substrate. The method includes the steps as follows. At first, a pad layer is formed over the substrate. A first stacked layer is then formed over the pad laye...	02/01/2000
6020240	Method to simultaneously fabricate the self-aligned silicided devices and ESD protection devices The present invention discloses a method to simultaneously fabricate the self-aligned silicided devices and ESD protective devices in a substrate. A functional region and a ESD protective region are defined on the substrate and each region has a gate stru...	02/01/2000
6008079	Method for forming a high density shallow trench contactless nonvolatile memory The present invention proposes a method for fabricating a high-density shallow trench contactless nonvolatile memory. First, a stacked pad oxide/silicon nitride layer is deposited on the substrate and the buried bit line region is defined by a photoresist...	12/28/1999
6001674	Method of eliminating buried contact trench in SRAM devices The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed over the substrate. A first silicon layer is then formed over. A buried contact opening is defined through the first silicon layer...	12/14/1999
5994747	MOSFETs with recessed self-aligned silicide gradual S/D junction The present invention includes a gate oxide. A gate is formed on the gate oxide. Undercut portions, formed under the gate. The substrate has recessed portions are adjacent to the gate. A silicon oxynitride layer is formed on the side walls of the gate and...	11/30/1999
5970342	Method of forming high capacitive-coupling ratio and high speed flash memories with a textured tunnel oxide The method of the present invention includes patterning a gate structure. Then, a polyoxide layer is formed on side walls of the gate structure. Then, silicon nitride side wall spacers is formed on the side walls of the gate structure. Then, source/drain ...	10/19/1999
5930617	Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction The present invention includes forming an oxide layer on a substrate. An undoped polysilicon layers is deposited by chemical vapor deposition on the gate oxide layer. Next, a silicon nitride layer is successively formed on the polysilicon layer to act as ...	07/27/1999
5920774	Method to fabricate short-channel MOSFETS with an improvement in ESD resistance A method to fabricate simultaneously a MOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The ESD protective devices are fabricated by using double diffused drain (DDD) ion implantation technology. In the functional regio...	07/06/1999
5913118	Method of manufacturing trench DRAM cells with self-aligned field plate A silicon oxide, a silicon nitride layer are patterned to define trenches region. Then, a recess portion is formed in the substrate. Subsequently, a second silicon oxide, a second silicon nitride layer are formed on the recess portion. Then, a glass layer...	06/15/1999
5905281	Draw cell with a fork-shaped capacitor A fork-shaped capacitor of a dynamic random access memory cell is disclosed. This capacitor includes a semiconductor layer (110), and a first dielectric layer (119) formed over the semiconductor layer. The capacitor also includes a first doped region (118...	05/18/1999
5888579	Method and apparatus for preventing particle contamination in a process chamber The present invention is concerned with a method and apparatus for preventing particle contamination in a semiconductor process chamber wherein a contaminant purge system is utilized which has a first end connected in fluid communication with a conduit co...	03/30/1999
5877056	Ultra-short channel recessed gate MOSFET with a buried contact Following with the formation of pad insulator layer and a stacked layer stacked, a gate insulator is formed within the defined gate insulator space. A lightly doped region is doped and the stacked layer and the pad insulator layer is removed. A semiconduc...	03/02/1999
5869374	Method to form mosfet with an inverse T-shaped air-gap gate structure A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate is disclosed. The T-shaped air-gap gate structure reduces the parasitic resistance and capacitance; hence device structure operation spe...	02/09/1999
5856226	Method of making ultra-short channel MOSFET with self-aligned silicided contact and extended S/D junction An ultra-short channel MOSFET with the self-aligned silicided contact and the extended ultra-shallow source/drain junction is formed. An extremely short gate region can be defined without being limited with the bottleneck of the existed lithography techno...	01/05/1999
5837588	Method for forming a semiconductor device with an inverse-T gate lightly-doped drain structure A method for forming an ultra-short channel device with an inverse-T gate lightly-doped drain (ITLDD) structure is disclosed. The method includes forming a silicon layer (14) over a semiconductor substrate (10), and forming a dielectric layer (16) on the ...	11/17/1998
5834353	Method of making deep sub-micron meter MOSFET with a high permitivity gate dielectric The method of the present invention includes forming a silicon oxynitride layer on a substrate. Then, a dielectric layer with high permitivity is deposited by chemical vapor deposition on the silicon oxynitride layer. Subsequently, a rapid thermal process...	11/10/1998

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Assignee: Texas Instruments-Acer Incorporated