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Dave Barry
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| Number | Title | Issue Date |
| 7154421 | DNL/INL trim techniques for comparator based analog to digital converters A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signa... | 12/26/2006 |
| 7098684 | High speed switch A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control sign... | 08/29/2006 |
| 7098700 | Low power output driver An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for c... | 08/29/2006 |
| 7095347 | Digitally trimmed DAC cell A digitally trimmed current source. The novel current source includes a first circuit for generating a current in response to an applied voltage and a resistance variable in response to a control signal, and a second circuit for supplying the control signal. The fir... | 08/22/2006 |
| 7088148 | Sample and hold circuit and bootstrapping circuits therefor A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current w... | 08/08/2006 |
| 7071781 | High speed, high resolution amplifier topology An amplifier. The novel amplifier includes a first circuit for receiving and amplifying an input signal and outputting an output signal, and a second circuit for supplying power to the first circuit, wherein the power supplied varies in accordance with variations in... | 07/04/2006 |
| 6975189 | On-chip multilayer metal shielded transmission line Multi-layer metal-shielded monolithic transmission lines are formed in side-by-side arrangement by depositing parallel planar thin film, conductive layers, separated by nonconductive separator layers to form a stack of alternating conductive and nonconductive layers... | 12/13/2005 |
| 6931083 | Low noise, low distortion, muxable Gilbert mixer signal processing system and method with AGC functionality A signal processing system and method. The inventive system includes a first circuit for distributing an input signal between two or more channels in a current mode of operation. A second circuit is disposed in each of the channels for processing the input signal an... | 08/16/2005 |
| 6891424 | Monolithic payload IF switch A crosspoint switch architecture (10). The inventive architecture (10) includes a monolithic substrate (11) on which a plurality (N) of electrical inputs are provided. In addition, a plurality (M) of electrical outputs are provided on the substr... | 05/10/2005 |
| 6882294 | Resistive ladder, summing node circuit, and trimming method for a subranging analog to digital converter A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input termin... | 04/19/2005 |
| 6879276 | Split cell bowtie digital to analog converter and method A DAC (10) including an operational amplifier (12) having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I1/2 -I4/2); and an arrangement (11) for switchably co... | 04/12/2005 |
| 6717450 | Monolithic I-load architecture for automatic test equipment An active load circuit for automatic test equipment that tests integrated circuits. The active load circuit includes a current source; a current sink; a current switching switching circuit having current source and current sink nodes respectively connected to the cu... | 04/06/2004 |