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| Number | Title | Issue Date |
| 7372497 | Effective method to improve sub-micron color filter sensitivity An image sensor device and method for forming said device are described. The image sensor structure comprises a substrate with photodiodes, an interconnect structure formed on the substrate, a color filter layer above the interconnect structure, a first microlens ar... | 05/13/2008 |
| 7358549 | Multi-layered metal routing technique In accordance with the objectives of the invention a new method and structure is provided for the creation of multiple overlying layers of interconnect metal. A channel is reserved for the creation of via interconnects, no vias are placed on metal lines. The metal l... | 04/15/2008 |
| 7282122 | Method and system for target lifetime A method and system for determining a lifetime of a target for a physical vapor deposition tool (302), has, a mapping table (304a) of criteria for a minimum accumulating rate of Δ wafers fabricated by Δ target life for a target in the tool; an... | 10/16/2007 |
| 7281230 | Method of using mixed multi-Vt devices in a cell-based design A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshol... | 10/09/2007 |
| 7274048 | Substrate based ESD network protection for a flip chip In accordance with the objectives of the invention a new arrangement is provided for ESD protection of mounted flip chips. In a first embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicate... | 09/25/2007 |
| 7271988 | Method and system to protect electrical fuses A method and system is disclosed for protecting electrical fuse circuitries. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a t... | 09/18/2007 |
| 7253071 | Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer pr... | 08/07/2007 |
| 7247915 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr... | 07/24/2007 |
| 7213186 | Memory built-in self test circuit with full error mapping capability A new built-in self-test circuit device for testing an embedded memory array is achieved. The device comprises a pattern generator unit that executes a testing sequence to automatically write and read locations in an embedded memory. A comparison unit compares data ... | 05/01/2007 |
