Assignee: Taiwan Semiconductor Manufacturing Company

Location: Hsin-chu, TW
No. of patents: 333

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Number	Title	Issue Date
7972957	Method of making openings in a layer of a semiconductor device A method of making a semiconductor device including forming a first sacrificial layer over a first layer to be etched, the first sacrificial layer having a plurality of openings formed therethrough exposing a portion of the first layer; forming a first photoresist l...	07/05/2011
7910999	Method for four direction low capacitance ESD protection The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In add...	03/22/2011
7803257	Current-leveling electroplating/electropolishing electrode A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub...	09/28/2010
RE41697	Method of forming planarized coatings on contact hole patterns of various duty ratios A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at...	09/14/2010
7745904	Shallow trench isolation structure for semiconductor device A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing...	06/29/2010
7633127	Silicide gate transistors and method of manufacture A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferab...	12/15/2009
7625806	Method of fabricating a non-floating body device with enhanced performance Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of ...	12/01/2009
7615837	Lithography device for semiconductor circuit pattern generation General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ...	11/10/2009
7582934	Isolation spacer for thin SOI devices A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor ...	09/01/2009
7580129	Method and system for improving accuracy of critical dimension metrology A method for improving accuracy of optical critical dimension measurement of a substrate is provided. A process parameter that influences the refractive index and extinction coefficient of a thin film in the substrate is identified. A refractive index and extinction...	08/25/2009
7576374	Semiconductor device with robust polysilicon fuse A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed...	08/18/2009
7573736	Spin torque transfer MRAM device The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ ...	08/11/2009
7571421	System, method, and computer-readable medium for performing data preparation for a mask design A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correcti...	08/04/2009
7571021	Method and system for improving critical dimension uniformity A method for improving critical dimension of a substrate is provided. Manufacturing data of a plurality of critical dimension deviations corresponding to a plurality of areas on the substrate is collected. A plurality of sensitivity data corresponding to the plurali...	08/04/2009
7564556	Method and apparatus for lens contamination control The present disclosure provides a method for measuring lens contamination in a lithography apparatus. The method includes imaging an asymmetric pattern utilizing a lens system and measuring an alignment offset of the asymmetric pattern associated with the lens syste...	07/21/2009
7563653	ESD protection for high voltage applications An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at l...	07/21/2009
7547605	Microelectronic device and a method for its manufacture Provided are a microelectronic device and a method for its manufacture. In one example, the method includes providing a semiconductor substrate layer having a first material (e.g., silicon or silicon germanium). An insulating layer is formed on the semiconductor sub...	06/16/2009
7545001	Semiconductor device having high drive current and method of manufacture therefor A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one...	06/09/2009
7538025	Dual damascene process flow for porous low-k materials A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is fo...	05/26/2009
7534725	Advanced process control for semiconductor processing An advanced process control (APC) method for semiconductor fabrication is provided. A first substrate and a second substrate are provided. The first substrate and the second substrate include a dielectric layer. A first etch process parameter for the first substrate...	05/19/2009
7531399	Semiconductor devices and methods with bilayer dielectrics A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that i...	05/12/2009
7514730	Method of fabricating a non-floating body device with enhanced performance Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transist...	04/07/2009
7514348	Sidewall coverage for copper damascene filling A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed la...	04/07/2009
7505206	Microlens structure for improved CMOS image sensor sensitivity A method of manufacturing a microlens device by depositing a microlens material layer over a substrate that includes photo-sensors. The microlens material layer is then exposed and developed to define microlens material elements, including first microlens material e...	03/17/2009
7501227	System and method for photolithography in semiconductor manufacturing A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lo...	03/10/2009
7494830	Method and device for wafer backside alignment overlay accuracy A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on...	02/24/2009
7432192	Post ECP multi-step anneal/Htreatment to reduce film impurity A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a f...	10/07/2008
7407835	Localized slots for stress relieve in copper In accordance with the objectives of the invention a new method is provided for the creation of interconnect metal. Current industry practice is to uniformly add slots to wide and long copper interconnect lines, this to achieve improved CMP results. These slots, typ...	08/05/2008
7385249	Transistor structure and integrated circuit A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedur...	06/10/2008
7371629	N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the n...	05/13/2008
7364836	Dual damascene process A method of photoresist processing includes forming a first photoresist layer over composite layers of dielectric insulation and a top insulating layer and patterning a via hole pattern in the first photoresist layer by exposing to radiation of a first sensitivity. ...	04/29/2008
7359759	Method and system for virtual metrology in semiconductor manufacturing Provided are a method and a system for virtual metrology in semiconductor manufacturing. Process data and metrology data are received. Prediction data is generated based on the process data and metrology data using a learning control model. The system for virtual me...	04/15/2008
7358612	Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed ove...	04/15/2008
7358571	Isolation spacer for thin SOI devices A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor ...	04/15/2008
7357838	Relaxed silicon germanium substrate with low defect density A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided. ...	04/15/2008
7354847	Method of trimming technology A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature havi...	04/08/2008
7356656	Skew free control of a multi-block SRAM A multi-block SRAM memory system is described where a single global clock pulse is distributed to each memory block from the central control. At each SRAM memory block a local signal generator uses the globally distributed clock pulse to generate the required memory...	04/08/2008
7356550	Method for real time data replication A computer-based method of data replication of data in a programmable computer system having an ISAM database and a transaction log file, with the ISAM database having fields of tables and the transaction log file maintaining all files transactions of the ISAM datab...	04/08/2008
7356378	Method and system for smart vehicle route selection In one aspect a factory automation system for a wafer fab is provided. The factory automation system comprises: a manufacturing execution system (“MES”) for providing lot information; a material control system (“MCS”) for providing dynamic traffic informatio...	04/08/2008
7351936	Method and apparatus for preventing baking chamber exhaust line clog A method and apparatus involve providing a supply of nitrogen gas, heating the supply of nitrogen gas to a temperature, and ejecting the heated nitrogen gas through the exhaust line of the baking chamber on a periodic basis. The temperature is between a temperature ...	04/01/2008

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Assignee: Taiwan Semiconductor Manufacturing Company