Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.

Location: Hsin-Chu, TW
No. of patents: 479

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Number	Title	Issue Date
8184896	Methods of determining quality of a light source Methods for determining a quality of a light source applied to a photolithographic process are provided. An image sensor array is exposed to a light from a light source. Addresses and respective intensities corresponding to a plurality of locations on a pupil map re...	05/22/2012
8183914	Constant Gm circuit and methods Structures and methods for providing a temperature independent constant current reference are provided. A constant Gm circuit is disclosed with embodiments including a voltage controlled resistor providing a current into a current mirror, the current mirror sinking ...	05/22/2012
8183910	Circuit and method for a digital process monitor A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or...	05/22/2012
8183667	Epitaxial growth of crystalline material A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which r...	05/22/2012
8183626	High-voltage MOS devices having gates extending into recesses of substrates An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart fr...	05/22/2012
8179647	ESD power clamp for high-voltage applications An ESD clamp includes a first power supply node; an ESD detection circuit coupled to the first power supply node and configured to detect an ESD event; and a bias circuit coupled to the first power supply node and configured to output a second power supply voltage t...	05/15/2012
8178930	Structure to improve MOS transistor on-breakdown voltage A novel MOS transistor structure and methods of making the same are provided. The structure includes a MOS transistor formed on a semiconductor substrate of a first conductivity type with a plug region of first conductivity type formed in the drain extension region ...	05/15/2012
8178437	Barrier material and process for Cu interconnect A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal ri...	05/15/2012
8174868	Embedded SRAM structure and chip An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is...	05/08/2012
8174867	Negative-voltage generator with power tracking for improved SRAM write ability An integrated circuit structure includes a static random access memory (SRAM) cell; a first power supply node connected to the SRAM cell, wherein the first power supply node is configured to provide a first positive power supply voltage to the SRAM cell; and a bit-l...	05/08/2012
8174129	Silicon-based thin substrate and packaging schemes A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting...	05/08/2012
8174124	Dummy pattern in wafer backside routing A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TS...	05/08/2012
8174091	Fuse structure An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-la...	05/08/2012
8174073	Integrated circuit structures with multiple FinFETs A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and s...	05/08/2012
8174071	High voltage LDMOS transistor An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreov...	05/08/2012
8173990	Memory array with a selector connected to multiple resistive cells An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive mem...	05/08/2012
8173551	Defect reduction using aspect ratio trapping Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls. ...	05/08/2012
8173540	Methods of forming silicide regions and resulting MOS devices A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electr...	05/08/2012
8173503	Fabrication of source/drain extensions with ultra-shallow junctions A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting ...	05/08/2012
8173499	Method of fabricating a gate stack integration of complementary MOS device A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal...	05/08/2012
8173491	Standard cell architecture and methods with variable design rules Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum ...	05/08/2012
8172641	CMP by controlling polish temperature A method for manufacturing integrated circuits on a wafer includes providing a facility-supplied room temperature solution; controlling the temperature of the facility-supplied room temperature solution to a desired temperature set point to generate a rinse solution...	05/08/2012
8172635	Alignment device and method for aligning apertures in different plates An alignment device for aligning a second aperture in a second plate with a first aperture in a first plate and an alignment method of utilizing the same. The alignment device includes a main body, a first part extending from the main body, and a second part extendi...	05/08/2012
8169256	Bandgap reference circuit with an output insensitive to offset voltage A circuit includes an operational amplifier including a first input and a second input. A first resistor has a first end coupled to the first input. A first bipolar transistor includes a first emitter coupled to a second end of the first resistor, and a first base. ...	05/01/2012
8169076	Interconnect structures having lead-free solder bumps An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first sold...	05/01/2012
8169014	Interdigitated capacitive structure for an integrated circuit System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity,...	05/01/2012
8168501	Source/drain strained layers A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Furth...	05/01/2012
8160830	Method of yield management for semiconductor manufacture and apparatus thereof A method of yield management for semiconductor manufacture and an apparatus thereof are provided. The method includes the following steps. Defect data of a layer of a semiconductor wafer is obtained, wherein the defect data includes sizes and locations of defects wi...	04/17/2012
8159035	Metal gates of PMOS devices having high work functions A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The ref...	04/17/2012
8158475	Gate electrodes of HVMOS devices having non-uniform doping concentrations A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying...	04/17/2012
8158474	Semiconductor device with localized stressor A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-indu...	04/17/2012
8158456	Method of forming stacked dies The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wa...	04/17/2012
8158306	Method and system for combining photomasks to form semiconductor devices A photomask set includes at least two masks that combine to form a device pattern in a semiconductor device. Orthogonal corners may be produced in a semiconductor device pattern to include one edge defined by a first mask and an orthogonal edge defined by a second m...	04/17/2012
8156161	System and method for displaying data on a thin client A thin-client user interface includes a user interface and an application server. The user interface is executed on a client device, such as a personal computer having a display. The user interface includes a client application for displaying data. The application s...	04/10/2012
8154107	Semiconductor device and a method of fabricating the device A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress...	04/10/2012
8154051	MOS transistor with in-channel and laterally positioned stressors A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced tran...	04/10/2012
8153350	Method and material for forming high etch resistant double exposure patterns The present invention includes a lithography method comprising forming a first patterned resist layer including at least one opening therein over a substrate. A protective layer is formed on the first patterned resist layer and the substrate whereby a reaction occur...	04/10/2012
8152048	Method and structure for adapting solder column to warped substrate A multiple substrate system, a method, and structure for adapting solder volume to a warped module. An illustrative embodiment comprises a method for joining a first substrate to a second substrate. A deviation from a nominal gap between the first substrate and the ...	04/10/2012
8148826	Three-dimensional integrated circuits with protection layers A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and ...	04/03/2012
8148797	Chip pad resistant to antenna effect and method A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate e...	04/03/2012

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Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.