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| Number | Title | Issue Date |
| 8101340 | Method of inhibiting photoresist pattern collapse A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist laye... | 01/24/2012 |
| 8099861 | Current-leveling electroplating/electropolishing electrode A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub... | 01/24/2012 |
| 8021992 | High aspect ratio gap fill application using high density plasma chemical vapor deposition A high density plasma chemical vapor deposition process including exciting gas mixture to create a plasma including ions, and directing the plasma into a dense region above the upper surface of the semiconductor wafer, heating the wafer using an additional heat sour... | 09/20/2011 |
| 8021566 | Method for pre-conditioning CMP polishing pad An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the... | 09/20/2011 |
| 7910014 | Method and system for improving wet chemical bath process stability and productivity in semiconductor manufacturing A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentratio... | 03/22/2011 |
| 7714414 | Method and apparatus for polymer dielectric surface recovery by ion implantation In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the ... | 05/11/2010 |
| 7713380 | Method and apparatus for backside polymer reduction in dry-etch process A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method furt... | 05/11/2010 |
| 7545045 | Dummy via for reducing proximity effect and method of using the same A dummy via design for a dual damascene structure has a dielectric layer on a substrate, a dual damascene structure filled with a conductive material and inlaid in the dielectric layer, and a dummy via structure filled with a non-conductive material and inlaid in th... | 06/09/2009 |
| 7446034 | Process for making a metal seed layer An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition. ... | 11/04/2008 |
| 7446056 | Method for increasing polysilicon grain size The present invention relates to a method for increasing the grain size of a polysilicon layer, which includes exposing a silicon oxide wafer in a deposition chamber to an amount, effective for the purpose, of nitrogen at a flow rate of at least about 240 standard l... | 11/04/2008 |
| 7446424 | Interconnect structure for semiconductor package A semiconductor device includes a semiconductor substrate having top and bottom surfaces, the top surface having at least one device region thereon. At least one trench opening is formed through the substrate from the bottom surface and connecting to the device regi... | 11/04/2008 |
| 7423306 | CMOS image sensor devices A pixel comprises a substrate comprising a first well region formed in a top portion of the substrate, having a first conductivity type. A plurality of shallow trench isolation (STI) structures is formed in the first well region of the substrate, defining a pixel re... | 09/09/2008 |
| 7388796 | Method for testing memory under worse-than-normal conditions A method for testing a memory with cell plates and bit-line plates comprises putting the memory in a test mode, applying a test pattern to the memory, then providing a first voltage higher than Vdd/2 to the cell plate when writing a ‘1’ to a predetermined cell, ... | 06/17/2008 |
| 7256120 | Method to eliminate plating copper defect A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning ... | 08/14/2007 |
| 7241099 | Center ball O-ring A self-retaining O-ring having at least two radial struts connectively extending from inside surfaces to a central sphere-shaped retainer. The top surfaces of the radial struts are formed below the top surfaces of the O-ring. The central sphere-shaped retainer is co... | 07/10/2007 |
| 7227218 | Method and system for forming source regions in memory devices A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide lay... | 06/05/2007 |
| 7208331 | Methods and structures for critical dimension and profile measurement Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering metho... | 04/24/2007 |
| 7190626 | Memory system with bit-line discharging mechanism A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to ... | 03/13/2007 |
| 7189650 | Method and apparatus for copper film quality enhancement with two-step deposition The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for... | 03/13/2007 |
| 7183150 | Resist protect oxide structure of sub-micron salicide process In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet... | 02/27/2007 |
| 7180227 | Piezoelectric o-ring transducer An o-ring sealing device, molded with an imbedded piezoelectric element, for use in vacuum systems. The imbedded element, of a circumferential length, has an oblong cross-sectional shape, the oblong shape having a pair of ends for externally connecting to a signal p... | 02/20/2007 |
| 7179663 | CDA controller and method for stabilizing dome temperature A domed plasma reactor chamber uses an antenna driven by RF energy which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary... | 02/20/2007 |
| 7175951 | Two mask in-situ overlay checking method A method for in-situ overlay accuracy checking using a first mask having a first pattern and a second mask having a second pattern to expose a layer of photosensitive material formed on a wafer. The first pattern and the second pattern are exposed in the layer of ph... | 02/13/2007 |
| 7173259 | Automatically aligning objective aperture for a scanning electron microscope An automatically aligning objective aperture assembly for a CDSEM includes a plate that is moveable in X and Y directions relative to an electron beam generated by the SEM. The plate defines one or more objective apertures. Encoders and motors are provided for affec... | 02/06/2007 |
| 7153755 | Process to improve programming of memory cells A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom ant... | 12/26/2006 |
| 7154285 | Method and apparatus for providing PCB layout for probe card An effective and easy to fabricate method to test multiple integrated circuit device designs using a single, probe card design is provided. A universal, probe card design is disclosed herein to test a plurality of integrated circuit devices at the wafer level. Integ... | 12/26/2006 |
| 7153768 | Backside coating for MEMS wafer A transparent substrate has a micro electro-mechanical system (MEMS) on a first side of the substrate. An opaque layer is formed on a second side of the transparent substrate opposite the first side. The opaque layer comprises a first material that is removable by a... | 12/26/2006 |
| 7151271 | System and method for passing high energy particles through a mask A method and system is disclosed for concentrating high energy particles on a predetermined area on a target semiconductor substrate. A high energy source for generating a predetermined amount of high energy particles, and an electro-magnetic radiation source for ge... | 12/19/2006 |
| 7142043 | On chip word line voltage with PVT tracking for memory embedded in logic process The present disclosure is directed toward regulation of voltage for semiconductor memories. In an embodiment, a circuit for providing a controlled voltage level comprises a PMOS transistor coupled to a first voltage coupler (VPP), the gate of the PMOS tra... | 11/28/2006 |
| 7119600 | Wide common mode high-speed differential receiver using thin and thick gate oxide MOSFETS in deep-submicron technology A high speed receiver circuit is disclosed with a high supply voltage and operable with other circuits operating at a low supply voltage. The receiver circuit comprises first and second differential input signals controlling first and second current switches. It als... | 10/10/2006 |
| 7117460 | Method for physical parameter extraction for transistor model A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is... | 10/03/2006 |
| 7105439 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr... | 09/12/2006 |
| 7098119 | Thermal anneal process for strained-Si devices A method is disclosed for forming a semiconductor device using strained silicon. After forming a first substrate material with a first natural lattice constant on a device substrate and a second substrate material with a second natural lattice constant on the first ... | 08/29/2006 |
| 7087528 | Chemical-mechanical polishing (CMP) process for shallow trench isolation A method of forming shallow trench isolation includes etching trenches through a nitride layer, a polysilicon layer, and a pad oxide layer and into a semiconductor substrate. The trenches are filled with an oxide layer. A silicon oxynitride layer is deposited overly... | 08/08/2006 |
| 7078283 | Process for providing ESD protection by using contact etch module A new process is provided for the creation of an ESD protection circuit. The invention starts with a first conventional gate electrode and a second gate electrode that is designated as being the gate electrode that provides the ESD protection function. The contact s... | 07/18/2006 |
| 7075472 | Averaging analog-to-digital converter with shared capacitor network An analog-to-digital converter has one or more first stage comparators for generating a set of first stage comparator digital outputs, and a set of first stage comparator analog outputs upon comparing a voltage input with a set of voltage references, a switch networ... | 07/11/2006 |
| 7071478 | System and method for passing particles on selected areas on a wafer A method and system is disclosed for directing charged particles on predetermined areas on a target semiconductor substrate. After aligning a wafer mask with a semiconductor wafer, with the wafer mask having one or more mask patterns thereon, the charged particles a... | 07/04/2006 |
| 7060400 | Method to improve photomask critical dimension uniformity and photomask fabrication process A method of fabricating a photomask having improved critical dimension (CD) uniformity that meets or exceeds 90 nanometer technology requirements. The method includes the steps of: providing a transparent substrate covered with a layer of opaque material and a layer... | 06/13/2006 |
| 7052374 | Multipurpose slurry delivery arm for chemical mechanical polishing An adjustable slurry dispensing device for use with a chemical mechanical polishing apparatus is disclosed. The slurry arm is pivotally connected to the polishing apparatus and has a slurry delivery assembly that is translatable along the length of the arm. This com... | 05/30/2006 |
| 7053647 | Method of detecting potential bridging effects between conducting lines in an integrated circuit A method and system for detecting a potential reliability problem cause by electrical bridging in an integrated circuit. A voltage difference is created between two conducting lines in the integrated circuit to accelerate the bridging effect for a predetermined peri... | 05/30/2006 |
