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| Number | Title | Issue Date |
| 7387855 | Anti-ESD photomask blank An anti-electrostatic discharge photomask blank for fabrication of an anti-electrostatic discharge photomask is disclosed. The anti-electrostatic discharge photomask blank includes a mask substrate, a conductive layer provided on the mask substrate and an opaque pat... | 06/17/2008 |
| 7387961 | Dual damascene with via liner A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in t... | 06/17/2008 |
| 7257023 | Hybrid non-volatile memory device The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell ar... | 08/14/2007 |
| 7247575 | Multi-step EBR process for photoresist removal An edge bead removal process is disclosed. The process includes providing a wafer having a feature layer, coating a photoresist on the feature layer, rotating the wafer, and removing an edge bead from the wafer by removing an edge bump portion from the edge bead and... | 07/24/2007 |
| 7214991 | CMOS inverters configured using multiple-gate transistors An inverter that includes a first multiple-gate transistor including a source connected to a power supply, a drain connected to an output terminal, and a gate electrode; a second multiple-gate transistor including a source connected to a ground, a drain connected to... | 05/08/2007 |
| 7098491 | Protection circuit located under fuse window A semiconductor device having a fuse window above a substrate, the semiconductor device has at least one fuse protection circuit located under the fuse window. The fuse protection circuit includes a fuse having a first end connected to a first voltage and a second e... | 08/29/2006 |
| 7042032 | Magnetoresistive (MR) magnetic data storage device with sidewall spacer layer isolation A magnetoresistive magnetic data storage product and a method for fabrication thereof both employ a magnetic data storage device formed over a substrate. The magnetic data storage device comprises a free magnetoresistive material layer separated from a pinned magnet... | 05/09/2006 |
| 6992361 | Deep well implant structure providing latch-up resistant CMOS semiconductor product A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a ... | 01/31/2006 |
| 6982134 | Multiple stepped aperture repair of transparent photomask substrates A method for repairing a transparent photomask substrate and a transparent photomask substrate repaired in accord with the method employ when eliminating a defect within a transparent photomask substrate a multi-stepped aperture having a series of progressive steps ... | 01/03/2006 |
| 6617221 | Method of making capacitors A method for manufacturing capacitors is disclosed. The method is applicable to a capacitor whose upper electrode area is smaller than the lower electrode area. It is featured in that a material, such as a TiN hard mask, is inserted between the convention... | 09/09/2003 |
| 6531752 | Stripe photodiode element with high quantum efficiency for an image sensor cell A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine ... | 03/11/2003 |
| 6472286 | Bipolar ESD protection structure The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To hand... | 10/29/2002 |
| 6444584 | Plasma etch method for forming composite silicon/dielectric/silicon stack layer A method for forming a patterned composite stack layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket first silicon layer. There is then formed forming upon the blanket first s... | 09/03/2002 |
| 6287172 | Method for improvement of tungsten chemical-mechanical polishing process A multi-step chemical-mechanical polishing method for improving tungsten chemical-mechanical polishing (CMP) process is provided in the present invention. The method comprises following steps. First, a wafer is placed on a first pad of a CMP system, where... | 09/11/2001 |
| 5945255 | Birefringent interlayer for attenuating standing wave photoexposure of a photoresist layer formed over a reflective layer A method for attenuating within a microelectronics fabrication a standing wave photoexposure of a photoresist layer formed upon a reflective layer, and a microelectronics fabrication employed within the method. To practice the method, there is first provi... | 08/31/1999 |
