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| Number | Title | Issue Date |
| 7464346 | Method for designing phase-lock loop circuits A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of in... | 12/09/2008 |
| 7463513 | Micro-machinery memory device A micro-motor memory device includes at least one rotor having at least one indicator for rotating about an axis; and at least one stator placed adjacent to the rotor for electromagnetically or physically engaging the rotor to rotate the indicator to at least one pr... | 12/09/2008 |
| 7463096 | Dynamic voltage and frequency management in integrated circuits This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, o... | 12/09/2008 |
| 7462894 | Electrical fuse device with dummy cells for ESD protection An electrical fuse device includes at least one electrical fuse cell having a first switch device serially coupled with an electrical fuse representing a logic value; and at least one dummy cell having a second switch device coupled to the first switch device via a ... | 12/09/2008 |
| 7462554 | Method for forming semiconductor device with modified channel compressive stress A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizo... | 12/09/2008 |
| 7460391 | Write VCCMIN improvement scheme A semiconductor memory is disclosed, which comprises a plurality of memory cells, at least one high voltage power supply (CVDD) line coupled to the plurality of memory cells for supplying power to the same, and at least one controllable discharging circuit coupled b... | 12/02/2008 |
| 7459792 | Via layout with via groups placed in interlocked arrangement Via layout with via groups placed in an interlocked arrangement for suppressing the crack propagation along the domain boundary between the via groups. A structure has a metal via pattern located in a dielectric layer and having a first via group and a second via gr... | 12/02/2008 |
| 7459386 | Method for forming solder bumps of increased height A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein ex... | 12/02/2008 |
| 7459344 | Method for forming micromachined structure The invention provides a method of fabricating a micromachined structure, and in particular to a method of forming a micro-electro-mechanical system (MEMS) structure. A thin silicon cantilevered or suspended structure used to make micromachined structures is first f... | 12/02/2008 |
| 7458051 | ECO cell for reducing leakage power A semiconductor structure including at least one spare cell is disclosed. The semiconductor structure includes a first conductive line coupled to a power supply, and a second conductive line coupled to a complementary power supply. At least one spare cell is decoupl... | 11/25/2008 |
| 7456507 | Die seal structure for reducing stress induced during die saw process A seal ring structure between an integrated circuit region and a scribe line is provided. In one embodiment, the seal ring structure comprises a substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermet... | 11/25/2008 |
| 7456093 | Method for improving a semiconductor device delamination resistance A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on ... | 11/25/2008 |
| 7456090 | Method to reduce UBM undercut A method of manufacturing a solder bump structure on a semiconductor device is provided. In one embodiment, a semiconductor substrate is provided having a bonding pad and a passivation layer formed thereabove, the passivation layer having an opening therein exposing... | 11/25/2008 |
| 7456079 | EPI wafer and method of making the same A method including forming alignment marks in an upper surface of a semiconductor wafer; selectively depositing a mask over the alignment marks leaving portions of the upper surface exposed; depositing an epitaxial layer over the exposed portions of the upper surfac... | 11/25/2008 |
| 7456066 | Variable width offset spacers for mixed signal and system on chip devices MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first o... | 11/25/2008 |
| 7453149 | Composite barrier layer A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed... | 11/18/2008 |
| 7453127 | Double-diffused-drain MOS device with floating non-insulator spacers A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of i... | 11/18/2008 |
| 7453122 | SOI MOSFET device with reduced polysilicon loading on active area Silicon-on-insulator (SOI) devices with reduced polysilicon loading on an active area uses at least one dielectric layer resistant to silicidation to separate at least one body contact region from source/drain regions, thus reducing gate capacitance and improving de... | 11/18/2008 |
| 7453121 | Body contact formation in partially depleted silicon on insulator device An SOI device (100) has a gate electrode with one or more additional gate regions (120), and oxygen or halogen ions (128) under the additional gate regions (120). The oxygen or halogen ions (128) form thicker gate oxide regions or ... | 11/18/2008 |
| 7452822 | Via plug formation in dual damascene process A method for forming a dual damascene structure in a semiconductor device manufacturing process where via plugs which may include a thickness portion of a plug filling material overlying the process surface is formed by diffusing an acid into a plug filling material... | 11/18/2008 |
| 7452805 | Aluminum based conductor for via fill and interconnect A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 μm2 and a PVD aluminum base conductor filled in the opening. ... | 11/18/2008 |
| 7449785 | Solder bump on a semiconductor substrate A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer... | 11/11/2008 |
| 7446398 | Bump pattern design for flip chip semiconductor package A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central... | 11/04/2008 |
| 7446050 | Etching and plasma treatment process to improve a gate profile A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are re... | 11/04/2008 |
| 7446042 | Method for silicide formation on semiconductor devices A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling sup... | 11/04/2008 |
| 7445159 | Dual trench alternating phase shift mask fabrication Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a mask layer, which is over a quartz layer, of the PSM is patterned according to a semiconductor design. The mask layer is dry etched according to deep trenches of a PSM... | 11/04/2008 |
| 7443010 | Matrix form semiconductor package substrate having an electrode of serpentine shape A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate inclu... | 10/28/2008 |
| 7439751 | Apparatus and method for testing conductive bumps An apparatus and method for testing conductive bumps are provided. An exemplary embodiment of a bump testing unit comprises a support substrate with two probes protruding one surface thereof. A digital detecting device is embedded in the support substrate, comprisin... | 10/21/2008 |
| 7436698 | MRAM arrays and methods for writing and reading magnetic memory devices A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signa... | 10/14/2008 |
| 7436043 | N-well and Nburied layer isolation by auto doping to reduce chip size A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the com... | 10/14/2008 |
| 7432578 | CMOS image sensor with enhanced photosensitivity A photosensitive device is disclosed which comprises a semiconductor substrate, at least one reverse biased device, such as a P-N junction diode formed in the semiconductor substrate, and at least one photosensitive layer disposed above the semiconductor substrate a... | 10/07/2008 |
| 7432576 | Grid metal design for large density CMOS image sensor A new grid metal design for image sensors is disclosed which is comprised of a semiconductor image sensor chip having a pixel region covering most of the chip and a logic circuit region on the chip periphery. The pixel region contains, an array of image pixels where... | 10/07/2008 |
| 7432181 | Method of forming self-aligned silicides A method of forming self-aligned silicides is described and applied to a substrate having an isolation area, which divides the substrate into a first area and a second area. A resist protective oxide layer is formed on the substrate, and subsequently a mask layer is... | 10/07/2008 |
| 7432168 | Method for fabricating semiconductor device with thin gate spacer A method for fabricating a transistor. A substrate having a gate electrode thereon and insulated therefrom is provided. A first gate spacer with a first dielectric material is formed on the sidewalls of the gate electrode. A liner with a second dielectric material i... | 10/07/2008 |
| 7432041 | Method and systems to print contact hole patterns A method for forming an arbitrary pattern of sub-micron contact holes in a substrate using a combination of interferometric photolithography and optical photolithography with a non-critical mask. The substrate is covered with a photosensitive material and is exposed... | 10/07/2008 |
| 7429795 | Bond pad structure Bond pad structures are presented. Some embodiments of the structure include a conductive conductor-insulator layer overlying a substrate. The conductive conductor-insulator layer includes a composite region having a conductor sub-region and insulator sub-region, wh... | 09/30/2008 |
| 7429769 | Recessed channel field effect transistor (FET) device A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealin... | 09/30/2008 |
| 7429542 | UV treatment for low-k dielectric layer in damascene structure An UV treatment for making a low-k dielectric layer having improved properties in a damascene structure. A low-k dielectric layer in a damascene structure is subjected to an UV treatment with He gas or H2 gas to eliminate etching damage to the exposed sur... | 09/30/2008 |
| 7429496 | Buried photodiode for image sensor with shallow trench isolation technology A buried photodiode with shallow trench isolation technology is formed in a semiconductor substrate of a first conductive type. A trench having a bottom portion and a sidewall portion is formed in the semiconductor substrate. An isolation region is formed on the bot... | 09/30/2008 |
| 7425486 | Method for forming a trench capacitor A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the f... | 09/16/2008 |
