Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 7679926 | Capacitors with insulating layer having embedded dielectric rods A circuit structure is provided. The circuit structure includes a capacitor including a top capacitor electrode; a bottom capacitor electrode parallel to the top capacitor electrode; and an insulating layer between the top and the bottom capacitor electrodes. The in... | 03/16/2010 |
| 7633165 | Introducing a metal layer between SiN and TiN to improve CBD contact resistance for P-TSV The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench... | 12/15/2009 |
| 7388187 | Cross-talk reduction through deep pixel well implant for image sensors An image sensor device includes a semiconductor substrate having a first type of conductivity, a semiconductor layer having the first type of conductivity formed on the semiconductor substrate, and pixels formed in the semiconductor layer. The semiconductor layer in... | 06/17/2008 |
| 7386539 | System, method, and user interface providing customized document portfolio management A system for customized document portfolio management. Corresponding methods and user interfaces are provided accordingly for allowing customized document portfolio management. In an preferred embodiment the system includes a document metadata database storing a plu... | 06/10/2008 |
| 7385252 | ESD protection for high voltage applications An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at l... | 06/10/2008 |
| 7384836 | Integrated circuit transistor insulating region fabrication method A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped wel... | 06/10/2008 |
| 7384802 | ESD protection device for high voltage An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage w... | 06/10/2008 |
| 7383530 | System and method for examining mask pattern fidelity A method and system is disclosed for examining mask pattern fidelity. A mask picture is generated from a first mask with a first OPC model applied to a mask design. The mask picture is converted into a mask based simulation file. A first simulation is conducted unde... | 06/03/2008 |
| 7382023 | Fully depleted SOI multiple threshold voltage application An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A se... | 06/03/2008 |
| 7382012 | Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective dielectric constant of dielectric layer A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value ov... | 06/03/2008 |
| 7381649 | Structure for a multiple-gate FET device and a method for its fabrication A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etc... | 06/03/2008 |
| 7381619 | Dual work-function metal gates A semiconductor device having dual work-function structures, such as dual work-function gate electrodes of transistors. In the preferred embodiment in which NMOS and PMOS transistors are formed on a semiconductor device, the transistors are initially formed with a d... | 06/03/2008 |
| 7381613 | Self-aligned MIM capacitor process for embedded DRAM A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive materia... | 06/03/2008 |
| 7378744 | Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed ove... | 05/27/2008 |
| 7378724 | Cavity structure for semiconductor structures A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be form... | 05/27/2008 |
| 7378720 | Integrated stress relief pattern and registration structure A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within... | 05/27/2008 |
| 7378308 | CMOS devices with improved gap-filling A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the ... | 05/27/2008 |
| 7375040 | Etch stop layer A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form... | 05/20/2008 |
| 7371662 | Method for forming a 3D interconnect and resulting structures A method for forming three-dimensional (3D) integrated circuits includes providing a first wafer comprising a silicon layer on a top surface of the first wafer, providing a second wafer comprising a silicon oxide layer on a top surface of the second wafer, bonding t... | 05/13/2008 |
| 7371671 | System and method for photolithography in semiconductor manufacturing A method for forming a semiconductor device includes forming a photoresist layer over a substrate and patterning the photoresist layer to form photoresist portions. A second layer is formed over the substrate in areas not covered by the photoresist portions and the ... | 05/13/2008 |
| 7372083 | Embedded silicon-controlled rectifier (SCR) for HVPMOS ESD protection A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain... | 05/13/2008 |
| 7372102 | Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided. ... | 05/13/2008 |
| 7372104 | High voltage CMOS devices A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that... | 05/13/2008 |
| 7372107 | SOI chip with recess-resistant buried insulator and method of manufacturing the same A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric laye... | 05/13/2008 |
| 7368379 | Multi-layer interconnect structure for semiconductor devices An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers ... | 05/06/2008 |
| 7368334 | Silicon-on-insulator chip with multiple crystal orientations A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation a... | 05/06/2008 |
| 7368303 | Method for temperature control in a rapid thermal processing system A method is disclosed for a multi-zone interference correction processing for a rapid thermal processing (RTP) system. This processing allows for improved calibration/tuning of RTP systems by accounting for zone coupling. The disclosed method includes establishing b... | 05/06/2008 |
| 7365396 | SOI SRAM products with reduced floating body effect A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region o... | 04/29/2008 |
| 7364957 | Method and apparatus for semiconductor device with improved source/drain junctions A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrat... | 04/29/2008 |
| 7365026 | CHsacrificial layer for cu/low-k interconnects A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition CxHy on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a... | 04/29/2008 |
| 7364961 | SRAM cell design for soft error rate immunity A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, a... | 04/29/2008 |
| 7365432 | Memory cell structure An SRAM device includes an SRAM cell in a deep NWELL region in a substrate. PWELL regions in the SRAM cell occupy less than about 65% of the cell area of the SRAM cell. A ratio of a longer side of a cell area of the SRAM cell to a shorter side of the SRAM cell is la... | 04/29/2008 |
| 7361986 | Heat stud for stacked chip package A semiconductor package assembly is presented. The assembly comprises a first chip and a second chip. The back surfaces of the first and the second chips are thermally attached through a die attach material. The front surface of the first chip is attached to a subst... | 04/22/2008 |
| 7361990 | Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantiall... | 04/22/2008 |
| 7359272 | Circuit and method for an SRAM with reduced power consumption A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circu... | 04/15/2008 |
| 7354524 | Method and system for processing multi-layer films A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during th... | 04/08/2008 |
| 7354623 | Surface modification of a porous organic material through the use of a supercritical fluid An organic layer, such as a porous low-K dielectric in an IC, contains pores open at its surface. To close the pores, the organic layer is contacted by a supercritical fluid that is a solvent for the layer. After a small amount of the surface and the wall of the ope... | 04/08/2008 |
| 7354830 | Methods of forming semiconductor devices with high-k gate dielectric A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric port... | 04/08/2008 |
| 7355262 | Diffusion topography engineering for high performance CMOS fabrication Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on t... | 04/08/2008 |
| 7355235 | Semiconductor device and method for high-k gate dielectrics A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material... | 04/08/2008 |
