Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Location: Hsin-Chu, TW
No. of patents: 831

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8184760	Adaptive elastic buffer for communications Circuit and method for an adaptive elastic buffer for receiving data including timing signals. Received data is recovered and stored in the adaptive elastic buffer, and a recovery clock pointer is increased to identify the next buffer location for stuffing received ...	05/22/2012
8183701	Structure of stacking scatterometry based overlay marks for marks footprint reduction The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality o...	05/22/2012
8183627	Hybrid fin field-effect transistor structures and related methods Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. ...	05/22/2012
8183580	Thermally-enhanced hybrid LED package components A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first bond pad and a second bond pad on a surface of the carrier chip and bonded onto the LED chip through flip-chip bonding, and a third bond pad an...	05/22/2012
8183579	LED flip-chip package structure with dummy bumps A light-emitting device (LED) package component includes an LED chip having a first active bond pad and a second active bond pad. A carrier chip is bonded onto the LED chip through flip-chip bonding. The carrier chip includes a first active through-substrate via (TS...	05/22/2012
8183578	Double flip-chip LED package components A light-emitting device (LED) package component includes an LED chip and a carrier chip. The carrier chip includes a first and a second bond pad on a surface of the carrier chip; and a third and a fourth bond pad on the surface of the carrier chip and electrically c...	05/22/2012
8183162	Method of forming a sacrificial layer The present disclosure provides a method for making a semiconductor device. The method includes forming a material layer on a substrate; forming a sacrificial layer on the material layer, where the material layer and sacrificial layer each as a thickness less than 1...	05/22/2012
8180141	Wafer repair system A system for wafer repair, comprising an inspection tool being capable of extracting a wafer image of a semiconductor wafer; a direct-writing tool being capable of locally exposing the semiconductor wafer; and an information processing module configured to compare t...	05/15/2012
8179536	Measurement of overlay offset in semiconductor processing A system for overlay offset measurement in semiconductor manufacturing including a radiation source, a detector, and a calculation unit. The radiation source is operable to irradiate an overlay offset measurement target. The detector is operable to detect a first re...	05/15/2012
8179516	Protective layer on objective lens for liquid immersion lithography applications Disclosed is an objective lens adapted for use in liquid immersion photolithography and a method for making such a lens. In one example, the objective lens has multiple lens elements, one of which includes a transparent substrate and a layer of protective coating (P...	05/15/2012
8178980	Bond pad structure A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid l...	05/15/2012
8178970	Strong interconnection post geometry A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint struc...	05/15/2012
8178422	Method of measurement in semiconductor fabrication Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device subst...	05/15/2012
8178289	System and method for photolithography in semiconductor manufacturing A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lo...	05/15/2012
8178287	Photoresist composition and method of forming a resist pattern A resist material utilized in photolithography patterning includes a first material, and a second material dispersed in the first material. The second material is capable of diffusing to a top surface of the resist material, and has an etch rate different from that ...	05/15/2012
8178280	Self-contained proximity effect correction inspiration for advanced lithography (special) A lithography method is disclosed. An exemplary lithography method includes providing an energy sensitive resist material on a substrate; providing a desired pattern; performing a lithography process on the substrate, wherein the lithography process includes exposin...	05/15/2012
8173548	Reverse planarization method A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first pho...	05/08/2012
8173518	Method of wafer bonding Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the f...	05/08/2012
8168529	Forming seal ring in an integrated circuit die The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utili...	05/01/2012
8164124	Photodiode with multi-epi films for image sensor The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate; a first epitaxy semiconductor layer disposed on the semiconductor substrate and having a first type of dopant and a first doping concen...	04/24/2012
8163655	Method for forming a sacrificial sandwich structure The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on a substrate; forming a second material layer on the first material layer; forming a sacrificial layer on the second material layer; form...	04/24/2012
8159029	High voltage device having reduced on-state resistance A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate bet...	04/17/2012
8158521	Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness...	04/17/2012
8158489	Formation of TSV backside interconnects by modifying carrier wafers An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch...	04/17/2012
8158335	High etch resistant material for double patterning The present invention includes a lithography method comprising forming a first patterned insist layer including at least one opening therein over a substrate. A water-soluble polymer layer is formed over the first patterned resist layer and the substrate, whereby a ...	04/17/2012
8154003	Resistive non-volatile memory device The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the me...	04/10/2012
8153526	High planarizing method for use in a gate last process A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop laye...	04/10/2012
8153523	Method of etching a layer of a semiconductor device using an etchant layer A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and ...	04/10/2012
8153498	Downsize polysilicon height for polysilicon resistor integration of replacement gate process A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gat...	04/10/2012
8153493	FinFET process compatible native transistor Provided is a top-channel only finFET device. The methods and devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, t...	04/10/2012
8153492	Self-aligned V-channel MOSFET Forming a high-κ/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-κ/metal gate process, after the sacrifici...	04/10/2012
8149562	System for decharging a wafer or substrate after dechucking from an electrostatic chuck A system for decharging a wafer or substrate disposed on an electrostatic chuck, includes a capacitance detector for measuring a capacitance between the electrostatic chuck and the wafer or substrate, and a decharging voltage calculator for calculating a decharging ...	04/03/2012
8148249	Methods of fabricating high-k metal gate devices Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-hi...	04/03/2012
8148232	Overlay mark enhancement feature Methods and apparatuses for alignment are disclosed. An exemplary method includes providing a substrate having a device region and an alignment region; forming a first material layer over the substrate; forming a device feature and a dummy feature in the first mater...	04/03/2012
8147909	Method of making and using alloy susceptor with improved properties for film deposition Provided is a method for processing a wafer that includes providing an alloy susceptor including an exterior surface and a wafer contact surface. The exterior surface of the alloy susceptor is treated to produce a roughness of the exterior surface. The roughened ext...	04/03/2012
8145337	Methodology to enable wafer result prediction of semiconductor wafer batch processing equipment A method to enable wafer result prediction from a batch processing tool, includes collecting manufacturing data from a batch of wafers processed in batch in the batch processing tool, to form a batch processing result; defining a degree of freedom of the batch proce...	03/27/2012
8143971	MEMS resonator A MEMS resonator, comprising a planar resonator body formed of two different materials with opposite sign temperature coefficient of Young's modulus. A first portion of one material extends across the full thickness of the resonator body. This provides a design whic...	03/27/2012
8143602	High-volume manufacturing massive e-beam maskless lithography system The present disclosure provides a maskless lithography apparatus. The apparatus includes a plurality of writing chambers, each including: a wafer stage operable to secure a wafer to be written and a multi-beam module operable to provide multiple radiation beams for ...	03/27/2012
8143131	Method of fabricating spacers in a strained semiconductor device The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on e...	03/27/2012
8142959	Method and apparatus for gating photomask contamination A photomask is provided that includes a transparent substrate, a mask pattern formed on a first area of the substrate, the mask pattern having one or more openings that allow light radiation to pass through and having one or more features formed of a first material,...	03/27/2012

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.