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| Number | Title | Issue Date |
| 7509599 | Method and apparatus for performing formal verification using data-flow graphs An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLM | 03/24/2009 |
| 7460535 | Device and method that allows single data recovery circuit to support multiple USB ports A method and apparatus for routing data in a device having a plurality of parts. A signal is received at a first port. A detection is made that the first port received the signal. Information contained in the signal is selectively routed from the first port to a dat... | 12/02/2008 |
| 7458059 | Model of sensitivity of a simulated layout to a change in original layout, and use of model in proximity correction A memory is encoded with a model of sensitivity of a distorted layout generated by simulation of a wafer fabrication process, with respect to a change in an original layout that is input to the simulation. The sensitivity model comprises an expression of convolution... | 11/25/2008 |
| 7458045 | Silicon tolerance specification using shapes as design intent markers Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to ... | 11/25/2008 |
| 7458040 | Resettable memory apparatuses and design Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of memory units; and a reset information propagation logic coupled to the re... | 11/25/2008 |
| 7457736 | Automated creation of metrology recipes An automated metrology recipe set up process is described for a manufacturing process, in which patterns to be formed on a device are defined using a design database. The design database is processed to produce a simulated image of a feature for use in a metrology t... | 11/25/2008 |
| 7454739 | Method and apparatus for determining an accurate photolithography process model One embodiment of the present invention provides a system that determines an accurate process model. During operation, the system receives process data. Next, the system receives an optical model which models an optical system of a photolithography process. The syst... | 11/18/2008 |
| 7454732 | Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a hierarchical resource estimation is performed based on a technology indep... | 11/18/2008 |
| 7454731 | Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height ... | 11/18/2008 |
| 7454551 | Reconstructing transaction order using clump tags A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decod... | 11/18/2008 |
| 7453083 | Negative differential resistance field effect transistor for implementing a pull up element in a memory cell A memory cell includes a storage capacitor and a negative differential resistance (NDR) field effect transistor (FET), wherein the NDR FET is connected between a high voltage source and the storage capacitor. A junction between the NDR FET and the storage capacitor ... | 11/18/2008 |
| 7454727 | Method and Apparatus for Solving Sequential Constraints Relates to automatic conversion of assumption constraints, used in circuit design verification, that model an environment for testing a DUT/DUV, where the assumptions specify sequential behavior. Such assumptions are converted, with the use of logic synthesis tools,... | 11/18/2008 |
| 7451412 | Speeding up timing analysis by reusing delays computed for isomorphic subcircuits One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist... | 11/11/2008 |
| 7451068 | Method and apparatus for generating an OPC segmentation based on modeled intensity gradients One embodiment of the invention provides a system that dissects edges of a layout of an integrated circuit to produce a segmentation of the layout for a subsequent optical proximity correction (OPC) operation. In order to perform the dissection, the system first per... | 11/11/2008 |
| 7444605 | Generating a base curve database to reduce storage cost An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set id... | 10/28/2008 |
| 7435513 | Design and layout of phase shifting photolithographic masks A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, comput... | 10/14/2008 |
| 7436008 | Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and indu... | 10/14/2008 |
| 7434187 | Method and apparatus to estimate delay for logic circuit optimization Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first ... | 10/07/2008 |
| 7430543 | Method of enforcing a contract for a CAD tool A method for enforcing a contract for a computer-aided-design (CAD) tool is provided. In this method, a first payment for the CAD tool is made in accordance with the contract. The first payment is associated with user access to the CAD tool. At this point, the CAD t... | 09/30/2008 |
| 7424380 | Method and apparatus for integrated distribution function capture Probability distribution functions (PDFs), of a periodic input data signal, can be used to provide eye-diagram information. An advantage of PDFs, over conventional approaches to eye-diagram collection, is that analog-to-digital conversion can be accomplished by the ... | 09/09/2008 |
| 7422841 | Exposure control for phase shifting photolithographic masks Mask and integrated circuit fabrication approaches are described to facilitate use of masks where substantially all of a layout is defined using phase shifting. Exposure settings including relative dosing between the phase shift mask and the trim masks are described... | 09/09/2008 |
| 7421678 | Assist feature placement using a process-sensitivity model One embodiment of the present invention provides a system that determines an assist feature placement. During operation, the system receives an initial assist feature placement for a layout. Next, the system determines assist feature perturbations using the initial ... | 09/02/2008 |
| 7421379 | Segmentation and interpolation of current waveforms A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output v... | 09/02/2008 |
| 7418640 | Dynamically reconfigurable shared scan-in test architecture A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chai... | 08/26/2008 |
| 7417888 | Method and apparatus for resetable memory and design approach for same A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupl... | 08/26/2008 |
| 7417451 | Leakage power management with NDR isolation devices A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device rai... | 08/26/2008 |
| 7415684 | Facilitating structural coverage of a design during design verification One embodiment of the present invention provides a method and a system that facilitates structural coverage of a design during a design verification process. During operation, the system receives a hardware description of the design, which contains one or more modul... | 08/19/2008 |
| 7415678 | Method and apparatus for synthesis of multimode X-tolerant compressor Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described. ... | 08/19/2008 |
| 7415402 | Simulation based PSM clear defect repair method and system Mask shops typically use carbon to repair any clear defects identified on a mask, irrespective of the type of mask. However, carbon can have different characteristics than the original patterning material on the mask. Therefore, a mask that is repaired using carbon ... | 08/19/2008 |
| 7415150 | Photomask image registration in scanning electron microscope imagery One embodiment of the present invention provides a system that computes translational differentials between a “perfect” image (henceforth called a database-image) and a scanned-image of a photomask. During operation, the system receives a noise-free database-ima... | 08/19/2008 |
| 7404168 | Detailed placer for optimizing high density cell placement in a linear runtime A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is us... | 07/22/2008 |
| 7403649 | System and method of providing mask defect printability analysis A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The def... | 07/22/2008 |
| 7400694 | Method and apparatus for eye-opening based optimization An eye opening measurement technique, that does not interrupt a receiver's normal operation, is used as a metric for optimizing any selected parameters of the receiver's operation. If eye opening size decreases, as a result of a change to a receiver parameter, the p... | 07/15/2008 |
| 7389479 | Formally proving the functional equivalence of pipelined designs containing memories One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a s... | 06/17/2008 |
| 7386820 | Method and apparatus for formally checking equivalence using equivalence relationships An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLM | 06/10/2008 |
| 7386053 | System and method of equalization of high speed signals In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includ... | 06/10/2008 |
| 7386433 | Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout One embodiment of the invention provides a system for speeding up an iterative process that simulates and, if necessary, corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the ta... | 06/10/2008 |
| 7383518 | Method and apparatus for performance metric compatible control of data transmission signals The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a differential signal as received by a receiver of a data transmission... | 06/03/2008 |
| 7382912 | Method and apparatus for performing target-image-based optical proximity correction A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next... | 06/03/2008 |
| 7382825 | Method and apparatus for integrated channel characterization A periodic broadband signal can be used to determine the S21 measurement for a channel by stimulating the channel across a spectrum of interest. The channel response to such broadband signal can be measured from undersampled data captured at the receiver.... | 06/03/2008 |
