Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5307478 | Method for inserting a path instruction during compliation of computer programs for processors having multiple functional units A method is provided for inserting a path instruction during compilation of computer programs for a processor having multiple functional resources. A path instruction is inserted in the order of object code instruction during the reordering of the instruc... | 04/26/1994 |
| 5276955 | Multilayer interconnect system for an area array interconnection using solid state diffusion A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electr... | 01/11/1994 |
| 5253359 | Control and maintenance subsystem network for use with a multiprocessor computer system Methods and apparatus for a maintenance and control system for sensing and controlling the numerous sections of a highly parallel multiprocessor system. The control and maintenance system communicates with all processors, all peripheral systems, all user ... | 10/12/1993 |
| 5251097 | Packaging architecture for a highly parallel multiprocessor system The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections... | 10/05/1993 |
| 5239629 | Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routin... | 08/24/1993 |
| 5202988 | System for communicating among processors having different speeds Communication among processors having differing operating speeds by providing wake queues in which slower processors can queue entries, access to which by multiple concurrent producers and multiple concurrent consumers is synchronized or controlled using ... | 04/13/1993 |
| 5202975 | Method for optimizing instruction scheduling for a processor having multiple functional resources A method for scheduling instructions for a processor having multiple functional resources wherein the reordering of the instructions is accomplished in response to a simulation of the run-time environment of the target machine. The simulation of the run-t... | 04/13/1993 |
| 5197130 | Cluster architecture for a highly parallel scalar/vector multiprocessor system A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access share... | 03/23/1993 |
| 5193192 | Vectorized LR parsing of computer programs A parser for parsing computer programs in a compiler has parsing tables arranged as linear vectors. In a reduction portion of the parser, a production table and a lookahead set table have paired entries at identical address offsets such that a one-to-one ... | 03/09/1993 |
| 5193187 | Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by all... | 03/09/1993 |
| 5187789 | Graphical display of compiler-generated intermediate database representation The graphical display of compiler intermediate database representation is produced to function as an aid in the development of highly optimizing compilers, the inspection of the compiler-generated intermediate representation, and the analysis of the effec... | 02/16/1993 |
| 5179702 | System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The so... | 01/12/1993 |
| 5175862 | Method and apparatus for a special purpose arithmetic boolean unit A special purpose arithmetic boolean unit is capable of performing extremely parallel bit-level boolean operations, particularly bit matrix manipulations. The special purpose arithmetic boolean unit is especially adapted for use in traditional vector proc... | 12/29/1992 |
| 5175856 | Computer with integrated hierarchical representation (IHR) of program wherein IHR file is available for debugging and optimizing during target execution A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. ... | 12/29/1992 |
| 5168570 | Method and apparatus for a multiple request toggling priority system A multiple request toggling (MRT) arbitration system for prioritizing requests to a set of shared resources by multiple requestors, especially requests by multiple processors to shared resources in a multiprocessor system. The MRT arbitration system assig... | 12/01/1992 |
| 5168547 | Distributed architecture for input/output for a multiprocessor system A distributed architecture for the input/output system for a multiprocessor system provides for equal and democratic access to all shared hardware resources by both the processors and the external interface ports of the multiprocessor system. This allows ... | 12/01/1992 |
| 5165038 | Global registers for a multiprocessor system Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated w... | 11/17/1992 |
| 5159678 | Method for efficient non-virtual main memory management The present invention provides a parallel memory scheduler for execution on a high speed highly parallel multiprocessor architecture. The operating system software provides intelligence and efficiency in swapping out process images to facilitate swapping ... | 10/27/1992 |
| 5107418 | Method for representing scalar data dependences for an optimizing compiler A method for representing scalar data dependencies for an optimizing compiler wherein a global scalar data dependence graph is created to represent all of the scalar objects in an entire program. The scalar data dependencies are represented as three chain... | 04/21/1992 |
| 5055707 | Method and apparatus for single step clocking on signal paths longer than a clock cycle An apparatus and method allows for starting and stopping of computer system clocks where the propagation length of signal paths exceed one clock cycle in length. A circular source buffer is provided at the source end of a signal path and saves the data pr... | 10/08/1991 |
