Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 5712180 | EEPROM with split gate source side injection Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation.... | 01/27/1998 |
| 5471478 | Flash EEPROM array data and header file structure A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divide... | 11/28/1995 |
| 5438573 | Flash EEPROM array data and header file structure A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divide... | 08/01/1995 |
| 5436587 | Charge pump circuit with exponetral multiplication A charge pump circuit comprises a plurality of voltage doubler circuits connected together such that a first voltage output generated by a first portion of a kth one of the voltage doubler circuits is substantially equal to Vdd*2k and Vdd*2 | 07/25/1995 |
| 5430859 | Solid state memory system including plural memory chips and a serialized bus A memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated t... | 07/04/1995 |
| 5428621 | Latent defect handling in EEPROM devices A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector... | 06/27/1995 |
| 5422842 | Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells A method and circuit programs and automatically verifies the programming of selected EEPROM cells without alternating between programming and reading modes like prior art methods and circuitry. The circuitry includes a programming circuit and a bit line v... | 06/06/1995 |
| 5418752 | Flash EEPROM system with erase sector select A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased tog... | 05/23/1995 |
| 5396468 | Streamlined write operation for EEPROM system Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques incl... | 03/07/1995 |
| 5380672 | Dense vertical programmable read only memory cell structures and processes for making them A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provi... | 01/10/1995 |
| 5369615 | Method for optimum erasing of EEPROM Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM), An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses, Techniques incl... | 11/29/1994 |
| 5343063 | Dense vertical programmable read only memory cell structure and processes for making them A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provi... | 08/30/1994 |
| 5313421 | EEPROM with split gate source side injection Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation.... | 05/17/1994 |
| 5297148 | Flash eeprom system A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased tog... | 03/22/1994 |
| 5272669 | Method and structure for programming floating gate memory cells A novel method and structure are taught for narrowing the distribution of charge on the floating gates after electrical erasure of a population of cells. This allows faster programming following erasure. An additional recovery step is performed after eras... | 12/21/1993 |
| 5270979 | Method for optimum erasing of EEPROM Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques incl... | 12/14/1993 |
| 5200959 | Device and method for defect handling in semi-conductor memory A solid-state memory array such as an electrically erasable programmable read only memory (EEprom) or Flash EEprom array is used to store sequential data in a prescribed order. The memory includes a first information list containing addresses and defect t... | 04/06/1993 |
| 5198380 | Method of highly compact EPROM and flash EEPROM devices Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangemen... | 03/30/1993 |
| 5172338 | Multi-state EEprom read and write circuits and techniques Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between ... | 12/15/1992 |
| 5163021 | Multi-state EEprom read and write circuits and techniques Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between w... | 11/10/1992 |
| 5070032 | Method of making dense flash EEprom semiconductor memory structures An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting f... | 12/03/1991 |
