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| Number | Title | Issue Date |
| 7970597 | Event-driven emulation system A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies inpu... | 06/28/2011 |
| 7895027 | HDL re-simulation from checkpoints A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process ... | 02/22/2011 |
| 7739646 | Analog and mixed signal IC layout system A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by ne... | 06/15/2010 |
| 7703054 | Circuit emulation and debugging method A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory dev... | 04/20/2010 |
| 7603640 | Multilevel IC floorplanner To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The region... | 10/13/2009 |
| 7461310 | IC functional and delay fault testing An integrated circuit (IC) tester tests an IC having logic blocks that communicate through clocked devices arranged into scan chains. The tester organizes a low-speed IC functional test into a succession of test cycles, each of a uniform test cycle period, and can c... | 12/02/2008 |
| 7386823 | Rule-based schematic diagram generator A schematic diagram generator processes a netlist to generate a schematic diagram based on a set of placement rules, corresponding to a separate characteristic pattern of interconnected devices and specifying a constraint on relative placement within the schematic d... | 06/10/2008 |
| 7366652 | Method of programming a co-verification system A co-verification system includes a computer programmed to act as a simulator for simulating behavior of a first portion of an electronic device under test (DUT) by acquiring, processing and generating data representing DUT signals. The co-verification system also i... | 04/29/2008 |
| 7310786 | IC compaction system An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to port... | 12/18/2007 |
| 7283944 | Circuit simulation bus transaction analysis While simulating a circuit described by the netlist, a circuit simulator produces a dump file containing a set of waveform data sequences, each corresponding to a separate signal within the circuit, and representing states of its corresponding signal at a succession... | 10/16/2007 |
| 7257794 | Unit-based layout system for passive IC devices A computer-aided design tool generates a layout for a passive device, such as a resistor or a capacitor, to be incorporated into an integrated circuit. The layout is based on a model describing the passive device as being formed by a variable number of interconnecte... | 08/14/2007 |
| 7178123 | Schematic diagram generation and display system A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the sch... | 02/13/2007 |
| 7013457 | Prioritized debugging of an error space in program code A computer system has an input system and an output system. Program code to be debugged has a plurality of program code statements. The input system is utilized to indicate an error variable in the program code. The error variable has an error value that differs fro... | 03/14/2006 |
| 6980211 | Automatic schematic diagram generation using topology information A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines correspon... | 12/27/2005 |
| 6920620 | Method and system for creating test component layouts In a computer-implemented method and system for creating a test component layout, after creating a reference component layout that is composed of a set of polygonal working shapes, a plurality of shape parameters are defined for the working shapes of the reference c... | 07/19/2005 |
| 6366874 | System and method for browsing graphically an electronic design based on a hardware description language specification Hardware description language (HDL)-centered design system and methodology uses HDL specification effectively as master depository for design intent or knowledge. Through network browser, designers conveniently navigate or explore design graphically. Desi... | 04/02/2002 |
| 6321363 | Incremental simulation using previous simulation results and knowledge of changes to simulation model to achieve fast simulation time Prior simulation results and model changes are used to shorten re-simulation time in improved design verification methodology, wherein simulator is re-run on design revision. Accelerated incremental simulation scheme boosts engineer design and verificatio... | 11/20/2001 |
