Assignee: Spansion LLC

Location: Sunnyvale, CA
No. of patents: 679

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Number	Title	Issue Date
8183623	Dual charge storage node memory device and methods for fabricating such device A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. T...	05/22/2012
8183622	Flash memory device comprising bit-line contact region with dummy layer between adjacent contact holes A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width d...	05/22/2012
8179153	Probe apparatus, a process of forming a probe head, and a process of forming an electronic device A probing apparatus includes a set of conductors configured to contact a surface of a workpiece simultaneously. A processor activates subsets of the conductors to determine a four-point-probe parameter, wherein the subset is less than the set of conductors. Another ...	05/15/2012
8175528	Wireless mass storage flash memory Systems and/or methods are presented that can facilitate access of a memory device by the use of wireless communication technologies. A memory module is presented which combines memory with a wireless adapter component and a memory controller component to facilitate...	05/08/2012
8174107	Stacked semiconductor devices and a method for fabricating the same The present invention provides a semiconductor device that includes semiconductor packages arranged in a stacked configuration. A plurality of leads are drawn from the stacked semiconductor packages and folded around the outer shape of each semiconductor package suc...	05/08/2012
8171627	Method of forming an electronic device A process of forming an electronic device including forming a first ultraviolet (“UV”) blocking layer over a conductive feature, wherein the first UV blocking layer lies within 90 nm of the conductive structure; forming a first insulating layer over the first UV...	05/08/2012
8158534	Reduction of defects formed on the surface of a silicon oxynitride film Methods for reducing defects on the surface of a silicon oxynitride film are disclosed, in one embodiment, the methods include, forming a silicon oxynitride film on a semiconductor substrate and heating the silicon oxynitride film to increase a hydrophilicity of a s...	04/17/2012
8156272	Multiple communication channels on MMC or SD CMD line The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g. a controller in a cellular phone, a PDA...	04/10/2012
8148771	Semiconductor device and method to manufacture thereof A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which...	04/03/2012
8148770	Memory device with buried bit line structure A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than th...	04/03/2012
8144522	Erasing flash memory using adaptive drain and/or gate bias A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adj...	03/27/2012
8143664	Semiconductor device having lower leakage current between semiconductor substrate and bit lines A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substra...	03/27/2012
8143661	Memory cell system with charge trap A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.	03/27/2012
8140778	Apparatus and method for data capture using a read preamble A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL compone...	03/20/2012
8140746	Intelligent memory data management Systems and/or methods that facilitate data management on a memory device are presented. A data management component can log and tag data creating data tags. The data tags can comprise static metadata, dynamic metadata or a combination thereof. The data management c...	03/20/2012
8139763	Randomized RSA-based cryptographic exponentiation resistant to side channel and fault attacks Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates data encryption, data decryption, and/or generation of digital signatures, associated with messages. The cryptographic component inclu...	03/20/2012
8134853	High read speed electronic memory with serial array transistors Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at ...	03/13/2012
8133801	Method for forming a semiconducting layer with improved gap filling properties A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depo...	03/13/2012
8130955	Random number generation through use of memory cell activity Systems and/or methods that facilitate security of data are presented. A random number generation component generates random numbers based in part on electron activity in a select memory cell(s) to facilitate data security. Sensor components that are highly sensitiv...	03/06/2012
8130584	Semiconductor device and control method of the same The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10...	03/06/2012
8125018	Memory device having trapezoidal bitlines and method of fabricating same A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, w...	02/28/2012
8122204	Shadow write and transfer schemes for memory devices Systems and methods for controlling memory devices are disclosed. In one embodiment, a memory system comprises a memory controller for forwarding a command signal and an address signal and for receiving and forwarding a data signal, and a first memory device for rec...	02/21/2012
8122181	Systems and methods for enhancing a data store for handling semantic information Systems (100) and methods (300) for enhancing a data store (DS) addressable at a block level and interfaced with a host device (HD) via a memory controller (MC), which may comprise a VMCC (110, 210). The methods involve receiving an access opera...	02/21/2012
8119477	Memory system with protection layer to cover the memory gate stack and methods for forming same A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection l...	02/21/2012
8117521	Implementation of recycling unused ECC parity bits during flash memory programming Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory wi...	02/14/2012
8117445	Near field communication, security and non-volatile memory integrated sub-system for embedded portable applications An architecture is presented that facilitates integrating memory, security functionalities and near field communication (NFC) capabilities in a mobile device. A memory module is provided that comprises non-volatile memory that stores security software, sensitive dat...	02/14/2012
8116151	Multi-level storage algorithm to emphasize disturb conditions Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic sta...	02/14/2012
8114756	Method and manufacture for high voltage gate oxide formation after shallow trench isolation formation A method and manufacture for fabrication of flash memory is provided. In fabricating the periphery region of the flash memory, the low voltage gate oxides and high voltage gate oxides are grown to the same height as each other prior to STI etching. After STI etching...	02/14/2012
8114736	Integrated circuit system with memory system A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a meta...	02/14/2012
8110412	Integrated circuit wafer system with control strategy An integrated circuit wafer system includes an integrated circuit wafer, measuring thicknesses of the integrated circuit wafer, calculating a change in temperature ramp rates and thickness offsets for subsequent processing based on the temperature ramp rates for pri...	02/07/2012
8107294	Read mode for flash memory A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command inclu...	01/31/2012
8105098	Automated loading/unloading of devices for burn-in testing The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby ...	01/31/2012
8098521	Method of providing an erase activation energy of a memory device A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species ...	01/17/2012
8097961	Semiconductor device having a simplified stack and method for manufacturing thereof Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor c...	01/17/2012
8097518	Semiconductor device and manufacturing method therefor There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower...	01/17/2012
8094509	Apparatus and method for placement of boosting cell with adaptive booster scheme A memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pa...	01/10/2012
8094478	Nonvolatile memory device having a plurality of memory blocks A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously bet...	01/10/2012
8093698	Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H2. A gettering layer is provided on and in contact with the fir...	01/10/2012
8093680	Metal-insulator-metal-insulator-metal (MIMIM) memory device The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, a...	01/10/2012
8093646	Flash memory device and method of forming the same with improved gate breakdown and endurance The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the sub...	01/10/2012

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Assignee: Spansion LLC