Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 8164135 | Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality... | 04/24/2012 |
| 8154928 | Integrated flash memory systems and methods for load compensation Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the lo... | 04/10/2012 |
| 8148768 | Non-volatile memory cell with self aligned floating and erase gates, and method of making same A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends su... | 04/03/2012 |
| 8138524 | Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive... | 03/20/2012 |
| 8072815 | Array of non-volatile memory cells including embedded local and global reference cells and system An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a lo... | 12/06/2011 |
| 8067931 | Fast voltage regulators for charge pumps A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast sta... | 11/29/2011 |
| 8049535 | Sense amplifier for low voltage high speed sensing A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input o... | 11/01/2011 |
| 8020055 | Method and apparatus for testing the connectivity of a flash memory chip In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, th... | 09/13/2011 |
| 8018773 | Array of non-volatile memory cells including embedded local and global reference cells and system An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a lo... | 09/13/2011 |
| 7990773 | Sub volt flash memory system Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply vol... | 08/02/2011 |
| 7974136 | Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channe... | 07/05/2011 |
| 7970016 | Systems and methods for transmission and reception of data including frequency and channel code selection Systems and methods are disclosed for wireless transmission and reception of data including processing and buffering features. According to one or more exemplary aspects, there is provided a wireless audio receiver for receiving a plurality of packets of encoded aud... | 06/28/2011 |
| 7969239 | Charge pump circuit and a novel capacitor for a memory integrated circuit A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane an... | 06/28/2011 |
| 7927994 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between ... | 04/19/2011 |
| 7893684 | Integrated power detector with temperature compensation for fully-closed loop control An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit fo... | 02/22/2011 |
| 7848159 | Non-volatile memory systems and methods including page read and/or configuration features A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by... | 12/07/2010 |
| 7848140 | Flash memory array system including a top gate memory cell A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included... | 12/07/2010 |
| 7868604 | Fast voltage regulators for charge pumps A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast sta... | 01/11/2011 |
| 7868375 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between ... | 01/11/2011 |
| 7865141 | Chipset for mobile wallet system The invention presents a chipset for a mobile wallet system in a communication terminal having a SIM socket and a RFID antenna. The chipset includes a wallet module and a controller module. The wallet module has a contactless interface port coupled to the RFID anten... | 01/04/2011 |
| 7860470 | Cross coupled high frequency buffer A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buff... | 12/28/2010 |
| 7855583 | Sense amplifier for low voltage high speed sensing A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input o... | 12/21/2010 |
| 7852679 | Integrated flash memory systems and methods for load compensation Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the lo... | 12/14/2010 |
| 7852063 | Integrated power detector with temperature compensation for fully-closed loop control An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit fo... | 12/14/2010 |
| 7851846 | Non-volatile memory cell with buried select gate, and method of making same A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first porti... | 12/14/2010 |
| 7851273 | Method of testing an integrated circuit die, and an integrated circuit die In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not... | 12/14/2010 |
| 7839682 | Array and pitch of non-volatile memory cells An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied dur... | 11/23/2010 |
| 7831872 | Test circuit and method for multilevel cell flash memory A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. ... | 11/09/2010 |
| 7829459 | Method and apparatus for strapping two polysilicon lines in a semiconductor integrated circuit device A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. T... | 11/09/2010 |
| 7829404 | Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an el... | 11/09/2010 |
| 7826267 | Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged volta... | 11/02/2010 |
| 7825698 | Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing trans... | 11/02/2010 |
| 7816723 | Semiconductor memory array of floating gate memory cells with program/erase and select gates A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an el... | 10/19/2010 |
| 7808839 | Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the subst... | 10/05/2010 |
| 7800159 | Array of contactless non-volatile memory cells A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, an... | 09/21/2010 |
| 7790518 | Method of trimming semiconductor elements with electrical resistance feedback A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through th... | 09/07/2010 |
| 7784693 | Assembly of SIM card and RFID antenna A subscriber identity module (SIM) card includes: a printed circuit board; a circuit provided on the printed circuit board and capable of executing SIM and RFID functions; a set of circuit contacts provided on the printed circuit board, electrically connected to the... | 08/31/2010 |
| 7778080 | Flash memory array system including a top gate memory cell A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included... | 08/17/2010 |
| 7763492 | Method of making phase change memory device employing thermally insulating voids and sloped trench A phase change memory device, and method of making the same, that includes a trench formed in insulation material having opposing sidewalls that are inwardly sloping with trench depth. A first electrode is formed in the trench. Phase change memory material is formed... | 07/27/2010 |
| 7749779 | Landing pad for use as a contact to a conductive spacer A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are ad... | 07/06/2010 |
