Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 8185739 | Method and system for detecting successful authentication of multiple ports in a time-based roving architecture In one embodiment of the present invention, a method includes authenticating an HDCP transmitting device at a first port of an HDCP receiving device. A port of the HDCP receiving device is connected to a pipe of an HDCP architecture of the HDCP receiving device at a... | 05/22/2012 |
| 8176214 | Transmission of alternative content over standard device connectors Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is ope... | 05/08/2012 |
| 8160192 | Signal interleaving for serial clock and data recovery A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback... | 04/17/2012 |
| 8149711 | Data stream control for network devices A method and apparatus for data stream control for network devices. Some embodiments of an apparatus include a receiver to receive a token for a command associated with a stream of data, where the command is one of multiple command types. The token has a fixed size ... | 04/03/2012 |
| 8116240 | Bi-directional bridge circuit having high common mode rejection and high input sensitivity A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate diffe... | 02/14/2012 |
| 8099648 | Error detection in physical interfaces for point-to-point communications between integrated circuits An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first subs... | 01/17/2012 |
| 8090030 | Method, apparatus and system for generating and facilitating mobile high-definition multimedia interface A method, apparatus and system are provided for generating and facilitating Mobile High-Definition Multimedia Interface. In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel... | 01/03/2012 |
| 8086886 | Group power management of network devices A method and apparatus for group power management of network devices. Some embodiments of an apparatus include a power management module, where the power management module is to transition the apparatus from a normal state to a low power state. The apparatus include... | 12/27/2011 |
| 8086067 | Noise cancellation A technique for reducing noise in a digital video signal is disclosed. In one embodiment, the technique involves receiving a digital signal. The digital signal can be filtered thereby generating a filtered signal. The digital signal and the filtered signal can be mi... | 12/27/2011 |
| 8064508 | Equalizer with controllably weighted parallel high pass and low pass filters and receiver including such an equalizer An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (β), and a second branch including a high pass filter (HPF) and having another variable gain (α). Outputs of the branches in response to an input sign... | 11/22/2011 |
| 8036248 | Method, apparatus, and system for automatic data aligner for multiple serial receivers A method, apparatus and system for employing an automatic data aligner for multiple serial receivers in serial link technologies is provided. In one embodiment, converting a transmission data path of a single bit into a parallel bit via a data aligner, wherein the d... | 10/11/2011 |
| 8026726 | Fault testing for interconnections Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconn... | 09/27/2011 |
| 8004606 | Original scan line detection A technique for detecting original scan lines is disclosed. The technique involves receiving a deinterlaced signal with even scan lines and odd scan lines. After the deinterlaced signal is received, a determination is made as to whether the even scan lines or the od... | 08/23/2011 |
| 8001334 | Bank sharing and refresh in a shared multi-port memory device A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory... | 08/16/2011 |
| 7991096 | Data sampling method and apparatus using through-transition counts to reject worst sampling position A data sampling circuit that employs an oversampling clock to oversample a data signal, a phase tracking circuit for use in such a sampling circuit, and a receiver and system including such a sampling circuit. Preferably, phase tracking is implemented by systematica... | 08/02/2011 |
| 7984369 | Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data st... | 07/19/2011 |
| 7982798 | Edge detection A technique for deinterlacing an interlaced video stream is disclosed. A method according to the technique can involve calculating a gradient of image intensity and identifying an edge. A bin can be selected that encompasses the edge. An unknown pixel can be calcula... | 07/19/2011 |
| 7979589 | Method, apparatus, and system for port multiplier enhancement A method, apparatus and system are provided for enhancing port multipliers. In one embodiment, a port multiplier is configured to couple a network host with port multipliers. The port multiplier includes a top port multiplier to establish and maintain communication ... | 07/12/2011 |
| 7978099 | 17B/20B coding system A method, apparatus and system employing a 17B/20B coder is disclosed. The 17B/20B coder to receive an incoming stream including a 17B block and a 20B block, and partition the 17B block into first blocks, and partitioning the 20B into second blocks. The coder is fur... | 07/12/2011 |
| 7949863 | Inter-port communication in a multi-port memory device A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each po... | 05/24/2011 |
| 7937644 | Error detection in physical interfaces for point-to-point communications between integrated circuits An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in ... | 05/03/2011 |
| 7921231 | Discovery of electronic devices utilizing a control bus Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is ... | 04/05/2011 |
| 7911956 | Packet level prioritization in interconnection networks A method and apparatus for packet level prioritization in interconnection networks. An embodiment of an apparatus includes a transmitter to transmit a data stream to a recipient apparatus, the data stream including a plurality of data packets, the data packets inclu... | 03/22/2011 |
| 7908501 | Progressive power control of a multi-port memory device A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-po... | 03/15/2011 |
| 7904566 | Method, apparatus, and system for employing an enhanced port multiplier A method, apparatus and system for employing an enhanced port multiplier are provided. In one embodiment, a network host is configured to be coupled with a port multiplier in a network. The port multiplier is configured into being cascaded into being coupled with a ... | 03/08/2011 |
| 7903684 | Communications architecture for transmission of data between memory bank caches and ports A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area netwo... | 03/08/2011 |
| 7903550 | Bandwidth reservation for data flows in interconnection networks A method and apparatus for bandwidth reservation for data flows in interconnection networks. Some embodiments of an apparatus for transmitting a data stream include a transmitter to transmit a data stream to a recipient apparatus, the data stream including a plurali... | 03/08/2011 |
| 7900047 | Method and apparatus for encrypting data transmitted over a serial link A communication system including a transmitter, a receiver, and a serial link (for example, a TMDS-like link) in which video data (or other data) are encrypted, the encrypted data are transmitted from the transmitter to the receiver, and the transmitted data are dec... | 03/01/2011 |
| 7849339 | Power-saving clocking technique A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming le... | 12/07/2010 |
| 7847583 | Transmitter and receiver using asymmetric transfer characteristics in differential amplifiers to suppress noise An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The different... | 12/07/2010 |
| 7872498 | Current mode circuitry to modulate a common mode voltage In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a firs... | 01/18/2011 |
| 7856520 | Control bus for connection of electronic devices A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with ... | 12/21/2010 |
| 7844762 | Parallel interface bus to communicate video data encoded for serial data links In some embodiments, a device includes a bus, a parallel source, and a parallel sink. The parallel source is to provide parallel groups of signals including video signals to the bus, wherein the bus has a number of lanes that is fewer than a number of signals used t... | 11/30/2010 |
| 7840861 | Scan-based testing of devices implementing a test clock control structure (“TCCS”) Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed. In one embodiment, a method includes performing an intra-domain test to exercise a first subset of domains of the plurali... | 11/23/2010 |
| 7836223 | Operation of media interface to provide bidirectional communications Embodiments of the invention are generally directed to operation of a media interface to provide bidirectional communications. An embodiment of a method includes connecting a first device to a second device via a media interface, the media interface including a comm... | 11/16/2010 |
| 7831877 | Circuitry to prevent peak power problems during scan shift In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes ... | 11/09/2010 |
| 7831778 | Shared nonvolatile memory architecture A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a ... | 11/09/2010 |
| 7797536 | Cryptographic device with stored key data and method for using stored key data to perform an authentication exchange or self test In preferred embodiments, a cryptographic device in which two key sets are stored: a normal key set (typically unique to the device) and a test key set (typically used by each of a relatively large number of devices). The device uses the normal key set in a normal o... | 09/14/2010 |
| 7793179 | Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers Systems, structures and methods for generating a test clock for scan chains to implement scan-based testing of electronic circuits are disclosed. In one embodiment, a test clock control structure includes a programmable test clock controller. The programmable test c... | 09/07/2010 |
| 7782934 | Parameter scanning for signal over-sampling A method and apparatus for parameter scanning for signal over-sampling. An embodiment of an apparatus includes an equalizer to equalize received data values, and a sampler to over-sample the equalized data. The apparatus includes an eye monitor to generate informati... | 08/24/2010 |
