Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8164091 | Multi-purpose poly edge test structure Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate... | 04/24/2012 |
| 8158520 | Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding th... | 04/17/2012 |
| 8158512 | Atomic layer deposition method and semiconductor device formed by the same There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert p... | 04/17/2012 |
| 8149190 | Correcting brightness variations in organic electroluminescent panel An OLED display having a correction circuit for producing corrected image data in response to the first image data and in response to correction data to correct for brightness unevenness due to TFT variations; a memory for storing first image data or correction data... | 04/03/2012 |
| 8148272 | Application of millisecond heating source for surface treatment A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminan... | 04/03/2012 |
| 8143666 | Semiconductor device with amorphous silicon monos memory cell structure and method for manufacturing thereof A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielec... | 03/27/2012 |
| 8133751 | ONO spacer etch process to reduce dark current A method of forming a CMOS image sensor device. The method includes providing a semiconductor substrate having a P-type impurity characteristic. The semiconductor substrate includes a surface region. The method includes forming a gate oxide layer overlying the surfa... | 03/13/2012 |
| 8123918 | Method and a system for operating a physical vapor deposition process A method for fabricating semiconductor wafers using physical vapor deposition. The method includes maintaining a substrate on a susceptor in a chamber. The substrate has a face positioned within a vicinity of a target material, which is within the chamber. The targe... | 02/28/2012 |
| 8119479 | Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate and method of manufacture A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a n... | 02/21/2012 |
| 8114732 | Method for manufacturing twin bit structure cell with AlO/nano-crystalline Si layer A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying t... | 02/14/2012 |
| 8110502 | Method of improving adhesion strength of low dielectric constant layers A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally... | 02/07/2012 |
| 8106664 | System and method for conducting accelerated soft error rate testing An apparatus for a user to conduct an accelerated soft error test (ASER) on a semiconductor sample is provided. The apparatus comprises a first component for holding the radiation source, where the radiation source may be either an alpha-particle or neutron-particle... | 01/31/2012 |
| 8106423 | Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semicond... | 01/31/2012 |
| 8105920 | Semiconductor device with amorphous silicon mas memory cell structure and manufacturing method thereof A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric la... | 01/31/2012 |
| 8105899 | Method and structure for performing a chemical mechanical polishing process A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an up... | 01/31/2012 |
| 8105898 | Method and structure for performing a chemical mechanical polishing process A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an up... | 01/31/2012 |
| 8105897 | Method and structure for performing a chemical mechanical polishing process A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an up... | 01/31/2012 |
| 8101478 | TFT MONOS or SONOS memory cell structures A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or... | 01/24/2012 |
| 8093114 | Method for making split dual gate field effect transistor A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first pluralit... | 01/10/2012 |
| 8089153 | Method for eliminating loading effect using a via plug Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is charac... | 01/03/2012 |
| 8058175 | Method for planarization of wafer and method for formation of isolation structure in top metal layer The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer... | 11/15/2011 |
| 8058120 | Integration scheme for strained source/drain CMOS using oxide hard mask A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate... | 11/15/2011 |
| 8053907 | Method and system for forming conductive bumping with copper interconnection An integrated circuit system with one or more copper interconnects is provided. The one or more copper interconnects are in conductive contact with a substrate. The integrated circuit system includes a first dielectric layer, a copper material filling a first via th... | 11/08/2011 |
| 8053843 | Integrated electrostatic discharge (ESD) device A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS trans... | 11/08/2011 |
| 8053310 | Method for defect reduction for memory cell capacitors A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching proc... | 11/08/2011 |
| 8053178 | Mask-less method and structure for patterning photosensitive material using optical fibers A method for patterning objects, e.g., semiconductor wafer, glass plate, composite, etc. The method includes providing an object, which has an overlying layer of photosensitive material. The method includes selectively applying light through one or more fiber cores ... | 11/08/2011 |
| 8049308 | Bond pad for low K dielectric materials and method for manufacture for semiconductor devices A semiconductor device having an improved contact structure. The device has a semiconductor substrate and a plurality of gate structures formed on the substrate. The device has a first interlayer dielectric overlying the gate structures. The device has a first coppe... | 11/01/2011 |
| 8048705 | Method and structure for a CMOS image sensor using a triple gate process A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a... | 11/01/2011 |
| 8044668 | Method and system for calibrating measurement tools for semiconductor device manufacturing A method and system for calibrating a plurality of measurement systems. The method includes obtaining a first plurality of calibration standards. The first plurality of calibration standards is associated with a plurality of predetermined values. Additionally, the m... | 10/25/2011 |
| 8039402 | Methods for forming a gate and a shallow trench isolation region and for planarizating an etched surface of silicon substrate There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching ... | 10/18/2011 |
| 8030165 | Poly gate etch method and device for sonos-based flash memory A method for forming flash memory devices is provided. The method includes providing a semiconductor substrate, which comprises a silicon material and has a periphery region and a cell region. The method further includes forming an isolation structure between the ce... | 10/04/2011 |
| 8026540 | System and method for CMOS image sensing A system is provided for determining a color using a CMOS image sensor. The system includes an input port for receiving a user command. The system further includes an image sensor, an optical device that forms an image on the image sensor, and a processor. The image... | 09/27/2011 |
| 8026151 | Method with high gapfill capability for semiconductor devices A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, w... | 09/27/2011 |
| 8024139 | Method and computer code for statistical process control for censored production data A method for monitoring device characteristics of semiconductor integrated circuits. The device characteristics includes censored data and uncensored data. The method includes determining a plurality of minimum breakdown voltages numbered from 1 through N, respectiv... | 09/20/2011 |
| 7996689 | System and method for power control for ASIC device A system and method for power control for ASIC device is disclosed. According to an embodiment, the present invention provides a system for adjusting power consumption of an application specific integrated circuit (ASIC) device. The system includes a first buffer th... | 08/09/2011 |
| 7995165 | LCOS display unit and method for forming the same An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shie... | 08/09/2011 |
| 7991497 | Method and system for defect detection in manufacturing integrated circuits Method and system for defect detection in manufacturing integrated circuits. In an embodiment, the invention provides a method for identifying one or more sources for possible causing manufacturing detects in integrated circuits. The method includes a step for provi... | 08/02/2011 |
| 7989363 | Method for rapid thermal treatment using high energy electromagnetic radiation of a semiconductor substrate for formation of dielectric films A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface re... | 08/02/2011 |
| 7989341 | Dual damascence copper process using a selected mask A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection.... | 08/02/2011 |
| 7989309 | Method of improving a shallow trench isolation gapfill process A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally... | 08/02/2011 |
