Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7961494 | Non-volatile multi-level re-writable memory cell incorporating a diode in series with multiple resistors and method for writing same A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the ... | 06/14/2011 |
| 7955515 | Method of plasma etching transition metal oxides A method of plasma etching transition metal oxide thin films using carbon monoxide as the primary source gas. This permits carbonyl chemistries to be used at ambient temperature, without heating. ... | 06/07/2011 |
| 7944728 | Programming a memory cell with a diode in series by applying reverse bias A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivi... | 05/17/2011 |
| 7940554 | Reduced complexity array line drivers for 3D matrix arrays A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of t... | 05/10/2011 |
| 7935594 | Damascene process for carbon memory element with MIIM diode Forming a metal-insulator diode and carbon memory element in a single damascene process is disclosed. A trench having a bottom and a sidewall is formed in an insulator. A first diode electrode is formed in the trench during a single damascene process. A first insula... | 05/03/2011 |
| 7935553 | Method for fabricating high density pillar structures by double patterning using positive photoresist A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first ... | 05/03/2011 |
| 7928007 | Method for reducing dielectric overetch when making contact to conductive features In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is sel... | 04/19/2011 |
| 7927977 | Method of making damascene diodes using sacrificial material A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed materi... | 04/19/2011 |
| 7924602 | Method to program a memory cell comprising a carbon nanotube fabric element and a steering element A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged ele... | 04/12/2011 |
| 7923812 | Quad memory cell and method of making same A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity ... | 04/12/2011 |
| 7923305 | Patterning method for high density pillar structures A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photor... | 04/12/2011 |
| 7915164 | Method for forming doped polysilicon via connecting polysilicon layers The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the... | 03/29/2011 |
| 7915163 | Method for forming doped polysilicon via connecting polysilicon layers The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the... | 03/29/2011 |
| 7915095 | Silicide-silicon oxide-semiconductor antifuse device and method of making An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer. ... | 03/29/2011 |
| 7915094 | Method of making a diode read/write memory cell in a programmed state A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrical... | 03/29/2011 |
| 7910407 | Quad memory cell and method of making same A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity ... | 03/22/2011 |
| 7906392 | Pillar devices and methods of making thereof A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion ... | 03/15/2011 |
| 7902537 | Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a reversible resistance-switching element above the first conductor using a selective growth process; (3) forming a diode above ... | 03/08/2011 |
| 7897453 | Dual insulating layer diode with asymmetric interface state and method of fabrication An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a secon... | 03/01/2011 |
| 7888205 | Highly scalable thin film transistor Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate len... | 02/15/2011 |
| 7888200 | Embedded memory in a CMOS circuit and methods of forming the same In some aspects, a method of forming a memory circuit is provided that includes (1) forming a two-terminal memory element on a substrate between a gate layer and a first metal layer of the memory circuit; and (2) forming a CMOS transistor on the substrate, the CMOS ... | 02/15/2011 |
| 7887999 | Method of making a pillar pattern using triple or quadruple exposure Methods of making pillar shaped device array using a triple or quadruple exposure technique are described. A plurality of pillar shaped devices are formed arranged in a hexagonal or rectangular pattern. ... | 02/15/2011 |
| 7885091 | Limited charge delivery for programming non-volatile storage elements A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and rese... | 02/08/2011 |
| 7848145 | Three dimensional NAND memory A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate li... | 12/07/2010 |
| 7846785 | Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selec... | 12/07/2010 |
| 7846782 | Diode array and method of making thereof A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semicondu... | 12/07/2010 |
| 7846756 | Nanoimprint enhanced resist spacer patterning method A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template i... | 12/07/2010 |
| 7875871 | Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride In the present invention a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to ... | 01/25/2011 |
| 7871909 | Methods of using single spacer to triple line/space frequency Methods for forming patterns having triple the line frequency of a first pattern using only a single spacer are disclosed. For example, the first pattern is formed in a first and a second material using a lithographic process. Sidewall spacers are formed from a thir... | 01/18/2011 |
| 7870472 | Methods and apparatus for employing redundant arrays to configure non-volatile memory Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redu... | 01/11/2011 |
| 7870471 | Methods and apparatus for employing redundant arrays to configure non-volatile memory Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redu... | 01/11/2011 |
| 7868388 | Embedded memory in a CMOS circuit and methods of forming the same In some aspects, a memory circuit is provided that includes (1) a two-terminal memory element formed on a substrate; and (2) a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element. The two-terminal memory element is formed b... | 01/11/2011 |
| 7863951 | Methods for adaptive trip point detection Methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input ... | 01/04/2011 |
| 7863950 | Apparatus for adaptive trip point detection Apparatus are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the inpu... | 01/04/2011 |
| 7861058 | Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewriteable memory The embodiments described herein can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash—an erasable, non-volatile memory) without requiring a firmware upgrade, thereby ... | 12/28/2010 |
| 7859887 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located... | 12/28/2010 |
| 7859884 | Structure and method for biasing phase change memory array for reliable writing A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In... | 12/28/2010 |
| 7855119 | Method for forming polycrystalline thin film bipolar transistors A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germani... | 12/21/2010 |
| 7851851 | Three dimensional NAND memory A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined b... | 12/14/2010 |
| 7843729 | Methods and apparatus for using a configuration array similar to an associated data array Methods, apparatus, and systems for memories that include a data array and a configuration array adapted to store configuration information for configuring the data array, are disclosed. The data array and the configuration array include a plurality of wordlines and... | 11/30/2010 |
