Assignee: SYNOPSYS, INC.

Location: Mountain View, CA
No. of patents: 357

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Number	Title	Issue Date
8184897	Method and apparatus for determining an optical threshold and a resist bias One embodiment of the present invention provides techniques and systems for determining modeling parameters for a photolithography process. During operation, the system can receive a layout. Next, the system can determine an iso-focal pattern in the layout. The syst...	05/22/2012
8184757	Pattern agnostic on-die scope An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a rec...	05/22/2012
8181145	Method and apparatus for generating a floorplan using a reduced netlist One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced n...	05/15/2012
8181143	Method and apparatus for generating a memory-efficient representation of routing data Some embodiments provide a system for generating a memory-efficient representation of a sequence of electrically connected routing shapes. The memory-efficient representation represents the sequence of electrically connected routing shapes using a sequence of points...	05/15/2012
8181128	Method and apparatus for determining a photolithography process model which models the influence of topography variations One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a wafer. When the photolithography process exposes the wafer to a layo...	05/15/2012
8176456	Method and apparatus for computing dummy feature density for chemical-mechanical polishing One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation...	05/08/2012
8176452	Method and apparatus for circuit partitioning and trace assignment in circuit design Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a cir...	05/08/2012
8171441	Integrated circuit devices and methods and apparatuses for designing integrated circuit devices Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling...	05/01/2012
8166450	Methods and apparatus for compiling instructions for a data processor Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in...	04/24/2012
8166434	Integrated circuit devices and methods and apparatuses for designing integrated circuit devices Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling...	04/24/2012
8161442	Integrated circuit devices and methods and apparatuses for designing integrated circuit devices Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling...	04/17/2012
8161437	Method and apparatus for automated synthesis of multi-channel circuits Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sha...	04/17/2012
8161434	Statistical formal activity analysis with consideration of temporal and spatial correlations Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the seque...	04/17/2012
8161426	Method and system for sizing polygons in an integrated circuit (IC) layout One embodiment of the present invention provides a system that sizes a polygon in a layout. During operation, the system receives a polygon which is to be sized by a sizing amount. The system then selects one or more vertices of the polygon. Next, the system replace...	04/17/2012
8161424	Method and apparatus for modeling chemically amplified resists Some embodiments provide a system for accurately and efficiently modeling chemically amplified resist. During operation, the system can determine a quenched acid profile from an initial acid profile by applying multiple quenching models which are associated with dif...	04/17/2012
8160856	Using a serial profiler to estimate the performance of a parallel circuit simulation Some embodiments of the present invention provide a system that profiles a serial simulation of a circuit to estimate the performance of a parallel simulation of the circuit. During operation, the system profiles execution of module instances during a serial simulat...	04/17/2012
8159001	Graded junction high voltage semiconductor device A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with t...	04/17/2012
8156462	Verification technique including deriving invariants from constraints A method of performing formal verification on a design for an integrated circuit can include accessing a set of constraints for the design. These constraints can be partitioned based on their variables, wherein any overlapping variables can result in the conjoining ...	04/10/2012
8156457	Concurrent simulation of hardware designs with behavioral characteristics Simulating hardware includes generating a data flow representation of the hardware, based on a hardware description language (HDL) description. The data flow representation including compatibility information that preserves behavioral and synthesizable characteristi...	04/10/2012
8155611	GPS baseband architecture A GPS baseband architecture provides flexibility and power consumption and chip area usage advantages. The GPS baseband architecture includes a first stage having a preamplifier coupled to a low noise amplifier, which is coupled to a mixer. A PLL provides the mixer ...	04/10/2012
8151236	Steiner tree based approach for polygon fracturing Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points (vertices of the starting polygon having an interior angle greater th...	04/03/2012
8151228	Method and apparatus for automated circuit design Methods and apparatuses to automatically modify a circuit design (e.g., a synthesis solution) according to the sensitivity in design parameters with respect to the possible deviation in the subsequent implementation (e.g., placement and routing) of the circuit. In o...	04/03/2012
8150787	Enhancing performance of a constraint solver across individual processes One embodiment of the present invention provides a system that reuses information associated with a constraint solving operation for a problem domain. This system begins by receiving a constraint problem from the problem domain. Then, the system searches through a p...	04/03/2012
8146047	Automation method and system for assessing timing based on gaussian slack An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functio...	03/27/2012
8146032	Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into...	03/27/2012
8145442	Fast and accurate estimation of gate output loading Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electri...	03/27/2012
8141024	Temporally-assisted resource sharing in electronic systems Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded...	03/20/2012
8141007	Method and apparatus for identifying and correcting phase conflicts One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PS...	03/20/2012
8139411	pFET nonvolatile memory A non-volatile memory integrated circuit includes multiple memory cells, each memory cell including a first MOS transistor, a first control capacitor, and a first floating gate coupled to the first MOS transistor and the first control capacitor. A first read/write c...	03/20/2012
8136077	Timing-optimal placement, pin assignment, and routing for integrated circuits Techniques for timing-optimal placement, pin assignment, and routing for integrated circuits are described herein. According to one embodiment, a list of paths providing implementation possibilities is constructed. A means is provided for removing paths from the lis...	03/13/2012
8136063	Unfolding algorithm in multirate system folding Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit opera...	03/13/2012
8136054	Compact abbe's kernel generation using principal component analysis Some embodiments provide techniques for determining a set of Abbe's kernels which model an optical system of a photolithography process. During operation, the system can receive optical parameters (e.g., numerical aperture, wavelength, etc.) for the photolithography...	03/13/2012
8132142	Various methods and apparatuses to route multiple power rails to a cell Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials ...	03/06/2012
8132141	Method and apparatus for generating a centerline connectivity representation Some embodiments provide a system for generating a centerline connectivity representation for a set of routing shapes. During operation, the system can represent the set of routing shapes using a set of centerlines with endcap extensions. Note that an intersection b...	03/06/2012
8132128	Method and system for performing lithography verification for a double-patterning process One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a firs...	03/06/2012
8127113	Generating hardware accelerators and processor offloads System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automaticall...	02/28/2012
8125245	Circuitry for matching the up and down impedances of a voltage-mode transmitter Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs o...	02/28/2012
8122412	Shelding mesh design for an integrated circuit device Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling...	02/21/2012
8121825	Method and apparatus for executing a hardware simulation and verification solution One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can inclu...	02/21/2012
8112736	Differential voltage defectivity monitoring method A method uses a differential voltage response to identify fabrication process defects that would result if an IC design is fabricated (without re-designing to correct such defects). The method uses two stacks, whose respective outputs may be compared by a comparator...	02/07/2012

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Assignee: SYNOPSYS, INC.